Symbol: skl_ddb_entry
drivers/gpu/drm/i915/display/intel_cursor.c
593
static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
drivers/gpu/drm/i915/display/intel_cursor.c
624
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
100
const struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/intel_display.c
7017
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
drivers/gpu/drm/i915/display/intel_display_debugfs.c
655
struct skl_ddb_entry *entry;
drivers/gpu/drm/i915/display/intel_display_types.h
928
struct skl_ddb_entry ddb;
drivers/gpu/drm/i915/display/intel_display_types.h
933
struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/intel_display_types.h
935
struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/intel_plane.c
816
struct skl_ddb_entry ddb[I915_MAX_PLANES],
drivers/gpu/drm/i915/display/intel_plane.c
817
struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
drivers/gpu/drm/i915/display/intel_plane.c
948
struct skl_ddb_entry ddb[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/intel_plane.c
949
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/intel_wm_types.h
62
static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
drivers/gpu/drm/i915/display/intel_wm_types.h
67
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
drivers/gpu/drm/i915/display/intel_wm_types.h
68
const struct skl_ddb_entry *e2)
drivers/gpu/drm/i915/display/skl_universal_plane.c
779
static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
drivers/gpu/drm/i915/display/skl_universal_plane.c
829
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_universal_plane.c
831
const struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_universal_plane.h
15
struct skl_ddb_entry;
drivers/gpu/drm/i915/display/skl_watermark.c
1353
skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
drivers/gpu/drm/i915/display/skl_watermark.c
1361
const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
drivers/gpu/drm/i915/display/skl_watermark.c
1395
struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/skl_watermark.c
1428
const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
drivers/gpu/drm/i915/display/skl_watermark.c
1472
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
1512
struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
1514
struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_watermark.c
1551
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
1553
const struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_watermark.c
1579
const struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
1581
const struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_watermark.c
2392
static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
drivers/gpu/drm/i915/display/skl_watermark.c
2393
const struct skl_ddb_entry *b)
drivers/gpu/drm/i915/display/skl_watermark.c
2398
static void skl_ddb_entry_union(struct skl_ddb_entry *a,
drivers/gpu/drm/i915/display/skl_watermark.c
2399
const struct skl_ddb_entry *b)
drivers/gpu/drm/i915/display/skl_watermark.c
2410
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/skl_watermark.c
2411
const struct skl_ddb_entry *entries,
drivers/gpu/drm/i915/display/skl_watermark.c
2706
const struct skl_ddb_entry *old, *new;
drivers/gpu/drm/i915/display/skl_watermark.c
3057
struct skl_ddb_entry *ddb =
drivers/gpu/drm/i915/display/skl_watermark.c
3059
struct skl_ddb_entry *ddb_y =
drivers/gpu/drm/i915/display/skl_watermark.c
3760
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
drivers/gpu/drm/i915/display/skl_watermark.c
3881
struct skl_ddb_entry ddb[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/skl_watermark.c
3882
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
drivers/gpu/drm/i915/display/skl_watermark.c
3913
const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
drivers/gpu/drm/i915/display/skl_watermark.c
398
static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
drivers/gpu/drm/i915/display/skl_watermark.c
415
struct skl_ddb_entry *ddb)
drivers/gpu/drm/i915/display/skl_watermark.c
42
struct skl_ddb_entry ddb[I915_MAX_PIPES];
drivers/gpu/drm/i915/display/skl_watermark.c
434
struct skl_ddb_entry ddb;
drivers/gpu/drm/i915/display/skl_watermark.c
447
const struct skl_ddb_entry *entry)
drivers/gpu/drm/i915/display/skl_watermark.c
535
struct skl_ddb_entry ddb_slices;
drivers/gpu/drm/i915/display/skl_watermark.c
670
static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
drivers/gpu/drm/i915/display/skl_watermark.c
683
struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/skl_watermark.c
684
struct skl_ddb_entry *ddb_y,
drivers/gpu/drm/i915/display/skl_watermark.c
714
struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/skl_watermark.c
715
struct skl_ddb_entry *ddb_y,
drivers/gpu/drm/i915/display/skl_watermark.h
19
struct skl_ddb_entry;
drivers/gpu/drm/i915/display/skl_watermark.h
31
const struct skl_ddb_entry *entry);
drivers/gpu/drm/i915/display/skl_watermark.h
33
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
drivers/gpu/drm/i915/display/skl_watermark.h
34
const struct skl_ddb_entry *entries,