sja1105_xfer_u32
int sja1105_xfer_u32(const struct sja1105_private *priv,
rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
rc = sja1105_xfer_u32(priv, SPI_WRITE,
return sja1105_xfer_u32(priv, SPI_WRITE, regs->pcs_base[phy] + offset,
rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, ®, NULL);
rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, ®, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
rc = sja1105_xfer_u32(priv, SPI_READ, regs->mdio_100base_tx + reg,
return sja1105_xfer_u32(priv, SPI_WRITE, regs->mdio_100base_tx + reg,
rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
rc = sja1105_xfer_u32(priv, SPI_WRITE,
rc = sja1105_xfer_u32(priv, SPI_READ, regs->pcs_base[phy] + offset,
rc = sja1105_xfer_u32(priv, SPI_WRITE, regs->ptpclkrate, &clkrate32,
rc = sja1105_xfer_u32(priv, SPI_WRITE, regs->ptppindur,
return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &switch_reset, NULL);
rc = sja1105_xfer_u32(priv, SPI_READ, regs->port_control,
return sja1105_xfer_u32(priv, SPI_WRITE, regs->port_control,
return sja1105_xfer_u32(priv, SPI_WRITE, regs->ptpclkcorp,