sja1105_xfer_buf
int sja1105_xfer_buf(const struct sja1105_private *priv,
return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port],
rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port],
rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
rc = sja1105_xfer_buf(priv, SPI_WRITE, SJA1110_BASE_TIMER_CLK,
return sja1105_xfer_buf(priv, SPI_WRITE, SJA1110_BASE_MCSS_CLK,
rc = sja1105_xfer_buf(priv, SPI_READ, ops->addr, packed_buf,
rc = sja1105_xfer_buf(priv, SPI_WRITE, ops->addr, packed_buf,
rc = sja1105_xfer_buf(priv, SPI_WRITE, ops->addr, packed_buf,
rc = sja1105_xfer_buf(priv, SPI_READ, regs + c->offset, buf, size);
rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
rc = sja1105_xfer_buf(priv, rw, regs->ptp_control, buf,
rc = sja1105_xfer_buf(priv, SPI_READ, regs->ptpegr_ts[port],
rc = sja1105_xfer_buf(priv, SPI_READ, regs->status, packed_buf, 4);
rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->config,
rc = sja1105_xfer_buf(priv, SPI_READ, regs->vl_status + 2 * vlid, buf,