drivers/gpu/drm/amd/display/dc/dc_dp_types.h

520

union sink_status sink_status;/* 205h */

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

423

irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1020

uint8_t sink_status = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1037

if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1038

(sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1107

u8 sink_status;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1110

ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1116

return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0;

drivers/gpu/drm/i915/display/intel_psr.c

4434

static const char * const sink_status[] = {

drivers/gpu/drm/i915/display/intel_psr.c

4461

if (status < ARRAY_SIZE(sink_status))

drivers/gpu/drm/i915/display/intel_psr.c

4462

str = sink_status[status];