drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1430

u32 tmp = RREG32(sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1447

sdma[j] = RREG32(sdma_v7_1_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1468

sdma_v7_1_get_reg_offset(adev, index, regSDMA0_SDMA_QUEUE0_PREEMPT);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1515

u32 reg_offset = sdma_v7_1_get_reg_offset(adev, type, regSDMA0_SDMA_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1628

RREG32(sdma_v7_1_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

227

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

231

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

373

rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

375

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

376

ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

378

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

412

sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_TIMEOUT), 0x80);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

440

mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

442

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), mcu_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

471

rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

479

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

483

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

484

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

485

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

486

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

488

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

489

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

490

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

491

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

495

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

497

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

501

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

503

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

514

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

515

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

521

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

524

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

525

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

528

doorbell = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

529

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL_OFFSET));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

538

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

539

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

550

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

553

temp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_WATCHDOG_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

557

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_WATCHDOG_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

560

temp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

563

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

566

temp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_PAGE));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

571

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

575

temp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

578

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

583

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

585

ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

591

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

706

tmp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

708

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

710

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_BASE_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

712

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_BASE_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

715

tmp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_OP_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

717

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_OP_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

722

sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_OP_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

724

sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

754

tmp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

757

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

759

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_PREEMPT), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

891

m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, 0,