drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

105

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

121

sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

122

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

146

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

193

sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

194

sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

195

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

232

sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,