drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1510

u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1526

sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1527

sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1582

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1584

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1587

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1595

stat1_reg = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1603

f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1605

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1607

cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1609

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1624

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1626

WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1690

sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1691

sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1766

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1776

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1779

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1789

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1803

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1806

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1810

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1813

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1858

data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1863

data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1904

RREG32(sdma_v5_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

354

wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

356

wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

397

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

400

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

568

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

570

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

571

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

573

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

628

f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

634

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

636

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

638

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

642

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

671

f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

673

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

701

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

705

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

712

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

716

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

717

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

718

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

719

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

721

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

722

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

723

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

724

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

728

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

730

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

732

wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

737

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

741

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

743

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

748

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

750

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

757

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

760

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

762

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

766

doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

767

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

777

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

778

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

788

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

792

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

797

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

800

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

803

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

806

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

810

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

815

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

817

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

822

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

824

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

830

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

904

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

909

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

912

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

974

m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

985

m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,