si2165_writereg8
ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp);
ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01);
ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
return si2165_writereg8(state, reg, val);
ret = si2165_writereg8(state, regs[i].reg, regs[i].val);
return si2165_writereg8(state, REG_PLL_DIVL, divl);
ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02);
ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version);
ret = si2165_writereg8(state, REG_RST_CRC, 0x01);
ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01);
ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00);
ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01);
ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00);
ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07);
ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00);
ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00);
ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01);
ret = si2165_writereg8(state, REG_START_INIT, 0x01);
ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00);
ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00);
ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20);
ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01);
ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00);
ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00);
ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
ret = si2165_writereg8(state, REG_BER_RST, 0x01);
ret = si2165_writereg8(state,