scu_registers
writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
ihost->scu_registers = scu_base;
struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
*ptsg = &ihost->scu_registers->peg0.ptsg;
val = readl(&ihost->scu_registers->sdma.pdma_configuration);
writel(val, &ihost->scu_registers->sdma.pdma_configuration);
val = readl(&ihost->scu_registers->sdma.cdma_configuration);
writel(val, &ihost->scu_registers->sdma.cdma_configuration);
&ihost->scu_registers->peg0.pe[i].tl,
&ihost->scu_registers->peg0.pe[i].ll);
iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
&ihost->scu_registers->sdma.uf_header_base_address_lower);
&ihost->scu_registers->sdma.uf_header_base_address_upper);
&ihost->scu_registers->sdma.uf_address_table_lower);
&ihost->scu_registers->sdma.uf_address_table_upper);
writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
&ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
readl(&ihost->scu_registers->peg0.ptsg.control);
&ihost->scu_registers->peg0.ptsg.control);
&ihost->scu_registers->sdma.unsolicited_frame_queue_control);
&ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
&ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
struct scu_registers __iomem *scu_registers;
return ARRAY_SIZE(ihost->scu_registers->peg0.sgpio.output_data_select);
struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
void __iomem *scu_reg_base = ihost->scu_registers;