shadow_regs
u8 *shadow_regs __free(kfree) = kzalloc(ADXL355_SHADOW_REG_COUNT, GFP_KERNEL);
if (!shadow_regs)
shadow_regs, ADXL355_SHADOW_REG_COUNT);
} while (memcmp(shadow_regs, data->buffer.buf,
u8 val = max8660->shadow_regs[MAX8660_OVER1];
u8 selector = max8660->shadow_regs[reg];
u8 selector = max8660->shadow_regs[MAX8660_MDTV2];
u8 val = max8660->shadow_regs[MAX8660_OVER2];
u8 selector = (max8660->shadow_regs[MAX8660_L12VCR] >> shift) & 0xf;
max8660->shadow_regs[MAX8660_OVER1] = 5;
max8660->shadow_regs[MAX8660_ADTV1] =
max8660->shadow_regs[MAX8660_ADTV2] =
max8660->shadow_regs[MAX8660_SDTV1] =
max8660->shadow_regs[MAX8660_SDTV2] = 0x1b;
max8660->shadow_regs[MAX8660_MDTV1] =
max8660->shadow_regs[MAX8660_MDTV2] = 0x04;
max8660->shadow_regs[MAX8660_OVER1] |= 1;
max8660->shadow_regs[MAX8660_OVER1] |= 4;
max8660->shadow_regs[MAX8660_OVER2] |= 2;
max8660->shadow_regs[MAX8660_OVER2] |= 4;
u8 shadow_regs[MAX8660_N_REGS]; /* as chip is write only */
u8 reg_val = (max8660->shadow_regs[reg] & mask) | val;
max8660->shadow_regs[reg] = reg_val;
struct shadow_regs *shadow_regs;
ha->shadow_regs->req_q_out = cpu_to_le32(0);
ha->shadow_regs->rsp_q_in = cpu_to_le32(0);
ha->shadow_regs = NULL;
sizeof(struct shadow_regs) +
ha->shadow_regs = (struct shadow_regs *) (ha->queues + align +
return (uint16_t)le32_to_cpu(ha->shadow_regs->req_q_out);
return (uint16_t)le32_to_cpu(ha->shadow_regs->rsp_q_in);