arch/arm/include/asm/vdso/cp15.h

14

#define __ACCESS_CP15(CRn, Op1, CRm, Op2) \

arch/arm/include/asm/vdso/cp15.h

15

"mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32

arch/arm/include/asm/vdso/cp15.h

16

#define __ACCESS_CP15_64(Op1, CRm) \

arch/arm/include/asm/vdso/cp15.h

17

"mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64

arch/arm64/include/asm/kvm_nested.h

176

u8 CRm = sys_reg_CRm(instr);

arch/arm64/include/asm/kvm_nested.h

187

if (CRm == TLBI_CRm_nROS &&

arch/arm64/include/asm/kvm_nested.h

191

if ((CRm == TLBI_CRm_RIS || CRm == TLBI_CRm_ROS ||

arch/arm64/include/asm/kvm_nested.h

192

CRm == TLBI_CRm_RNS) &&

arch/arm64/include/asm/kvm_nested.h

202

u8 CRm = sys_reg_CRm(instr);

arch/arm64/include/asm/kvm_nested.h

213

if (CRm == TLBI_CRm_IPAIS || CRm == TLBI_CRm_IPAONS)

arch/arm64/include/asm/kvm_nested.h

216

if (CRm == TLBI_CRm_nROS &&

arch/arm64/include/asm/kvm_nested.h

220

if ((CRm == TLBI_CRm_RIS || CRm == TLBI_CRm_ROS ||

arch/arm64/include/asm/kvm_nested.h

221

CRm == TLBI_CRm_RNS) &&

arch/arm64/include/asm/sysreg.h

117

#define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \

arch/arm64/include/asm/sysreg.h

119

sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \

arch/arm64/kvm/emulate-nested.c

2442

encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2);

arch/arm64/kvm/hyp/nvhe/sys_regs.c

383

Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \

arch/arm64/kvm/sys_regs.c

1186

if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)

arch/arm64/kvm/sys_regs.c

1191

idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);

arch/arm64/kvm/sys_regs.c

1202

if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)

arch/arm64/kvm/sys_regs.c

1207

idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);

arch/arm64/kvm/sys_regs.c

1219

if (r->CRn == 9 && r->CRm == 13) {

arch/arm64/kvm/sys_regs.c

1234

} else if (r->CRn == 0 && r->CRm == 9) {

arch/arm64/kvm/sys_regs.c

1240

} else if (r->CRn == 14 && (r->CRm & 12) == 8) {

arch/arm64/kvm/sys_regs.c

1245

idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);

arch/arm64/kvm/sys_regs.c

1274

if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {

arch/arm64/kvm/sys_regs.c

1278

} else if (r->CRn == 14 && (r->CRm & 12) == 12) {

arch/arm64/kvm/sys_regs.c

1279

idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);

arch/arm64/kvm/sys_regs.c

1379

if (r->CRm & 0x2)

arch/arm64/kvm/sys_regs.c

2742

Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \

arch/arm64/kvm/sys_regs.c

3885

u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

3896

u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

3914

u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

3925

u8 CRm = sys_reg_CRm(instr);

arch/arm64/kvm/sys_regs.c

3931

if (CRm == TLBI_CRm_nROS &&

arch/arm64/kvm/sys_regs.c

3941

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

3962

u8 CRm = sys_reg_CRm(instr);

arch/arm64/kvm/sys_regs.c

3969

if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) &&

arch/arm64/kvm/sys_regs.c

3973

if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) &&

arch/arm64/kvm/sys_regs.c

3977

if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) &&

arch/arm64/kvm/sys_regs.c

4033

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4057

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4112

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4138

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4150

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4411

{ AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \

arch/arm64/kvm/sys_regs.c

4414

{ Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \

arch/arm64/kvm/sys_regs.c

4416

{ Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \

arch/arm64/kvm/sys_regs.c

4418

{ Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n }

arch/arm64/kvm/sys_regs.c

4421

{ AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \

arch/arm64/kvm/sys_regs.c

4431

{ Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },

arch/arm64/kvm/sys_regs.c

4433

{ Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4437

{ Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4440

{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },

arch/arm64/kvm/sys_regs.c

4442

{ Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },

arch/arm64/kvm/sys_regs.c

4445

{ Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4447

{ Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4452

{ Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4454

{ Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4457

{ Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },

arch/arm64/kvm/sys_regs.c

4469

{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4473

{ Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },

arch/arm64/kvm/sys_regs.c

4476

{ Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },

arch/arm64/kvm/sys_regs.c

4480

{ Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4483

{ Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4497

{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4500

{ Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4502

{ Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4504

{ Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4506

{ Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4508

{ Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4510

{ Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },

arch/arm64/kvm/sys_regs.c

4516

{ Op1( 0), CRm( 1), .access = trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4519

{ Op1( 0), CRm( 2), .access = trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4524

Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \

arch/arm64/kvm/sys_regs.c

4544

{ Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },

arch/arm64/kvm/sys_regs.c

4545

{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },

arch/arm64/kvm/sys_regs.c

4547

{ AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },

arch/arm64/kvm/sys_regs.c

4549

{ AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },

arch/arm64/kvm/sys_regs.c

4550

{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },

arch/arm64/kvm/sys_regs.c

4551

{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },

arch/arm64/kvm/sys_regs.c

4553

{ AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },

arch/arm64/kvm/sys_regs.c

4555

{ AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },

arch/arm64/kvm/sys_regs.c

4556

{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },

arch/arm64/kvm/sys_regs.c

4559

{ Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },

arch/arm64/kvm/sys_regs.c

4560

{ Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },

arch/arm64/kvm/sys_regs.c

4562

{ Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },

arch/arm64/kvm/sys_regs.c

4564

{ Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },

arch/arm64/kvm/sys_regs.c

4566

{ AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },

arch/arm64/kvm/sys_regs.c

4568

{ AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },

arch/arm64/kvm/sys_regs.c

4573

{ Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },

arch/arm64/kvm/sys_regs.c

4574

{ Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },

arch/arm64/kvm/sys_regs.c

4575

{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },

arch/arm64/kvm/sys_regs.c

4599

{ AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },

arch/arm64/kvm/sys_regs.c

4601

{ AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },

arch/arm64/kvm/sys_regs.c

4603

{ AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },

arch/arm64/kvm/sys_regs.c

4605

{ AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },

arch/arm64/kvm/sys_regs.c

4630

{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },

arch/arm64/kvm/sys_regs.c

4703

{ Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },

arch/arm64/kvm/sys_regs.c

4704

{ Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },

arch/arm64/kvm/sys_regs.c

4707

{ Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },

arch/arm64/kvm/sys_regs.c

4709

{ Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },

arch/arm64/kvm/sys_regs.c

4713

{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },

arch/arm64/kvm/sys_regs.c

4715

{ Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */

arch/arm64/kvm/sys_regs.c

4717

{ Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },

arch/arm64/kvm/sys_regs.c

4718

{ Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */

arch/arm64/kvm/sys_regs.c

4720

{ Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */

arch/arm64/kvm/sys_regs.c

4852

params.CRm = (esr >> 1) & 0xf;

arch/arm64/kvm/sys_regs.c

4904

params->CRm = 3;

arch/arm64/kvm/sys_regs.c

4996

if (params->CRm > 3)

arch/arm64/kvm/sys_regs.c

5049

(params.CRm || params.Op2 == 6 /* REVIDR */))

arch/arm64/kvm/sys_regs.c

5052

params.CRm == 0 && params.Op2 == 7 /* AIDR */)

arch/arm64/kvm/sys_regs.c

5350

params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)

arch/arm64/kvm/sys_regs.c

5561

(reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |

arch/arm64/kvm/sys_regs.c

893

return &dbg->dbg_bvr[rd->CRm];

arch/arm64/kvm/sys_regs.c

895

return &dbg->dbg_bcr[rd->CRm];

arch/arm64/kvm/sys_regs.c

897

return &dbg->dbg_wvr[rd->CRm];

arch/arm64/kvm/sys_regs.c

899

return &dbg->dbg_wcr[rd->CRm];

arch/arm64/kvm/sys_regs.h

121

p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, str_write_read(p->is_write));

arch/arm64/kvm/sys_regs.h

18

(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)

arch/arm64/kvm/sys_regs.h

203

if (i1->CRm != i2->CRm)

arch/arm64/kvm/sys_regs.h

204

return i1->CRm - i2->CRm;

arch/arm64/kvm/sys_regs.h

24

u8 CRm;

arch/arm64/kvm/sys_regs.h

244

#define CRm(_x) .CRm = _x

arch/arm64/kvm/sys_regs.h

250

CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \

arch/arm64/kvm/sys_regs.h

257

CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \

arch/arm64/kvm/sys_regs.h

34

.CRm = sys_reg_CRm(reg), \

arch/arm64/kvm/sys_regs.h

41

.CRm = ((esr) >> 1) & 0xf, \

arch/arm64/kvm/sys_regs.h

48

.CRm = ((esr) >> 1) & 0xf, \

arch/arm64/kvm/sys_regs.h

59

p->CRn == 0 && !(p->CRm & 0b1000));

arch/arm64/kvm/sys_regs.h

76

u8 CRm;

arch/arm64/kvm/trace_handle_exit.h

108

__entry->CRm = reg->CRm;

arch/arm64/kvm/trace_handle_exit.h

115

__entry->CRm, __entry->Op2,

arch/arm64/kvm/trace_handle_exit.h

96

__field(u8, CRm)

tools/arch/arm64/include/asm/sysreg.h

115

#define __SYS_BARRIER_INSN(CRm, op2, Rt) \

tools/arch/arm64/include/asm/sysreg.h

116

__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))

tools/testing/selftests/kvm/include/arm64/gic_v5.h

83

#define __GIC_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \

tools/testing/selftests/kvm/include/arm64/gic_v5.h

85

sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \