CS35L41_PLL_CLK_CTRL
{ CS35L41_PLL_CLK_CTRL, 0x00000430 }, // 3072000Hz, BCLK Input, PLL_REFCLK_EN = 1
case CS35L41_PLL_CLK_CTRL:
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,