arch/mips/bcm47xx/irq.c

91

set_vi_handler(2, bcm47xx_hw2_irqdispatch);

arch/mips/bcm47xx/irq.c

92

set_vi_handler(3, bcm47xx_hw3_irqdispatch);

arch/mips/bcm47xx/irq.c

93

set_vi_handler(4, bcm47xx_hw4_irqdispatch);

arch/mips/bcm47xx/irq.c

94

set_vi_handler(5, bcm47xx_hw5_irqdispatch);

arch/mips/bcm47xx/irq.c

95

set_vi_handler(6, bcm47xx_hw6_irqdispatch);

arch/mips/bcm47xx/irq.c

96

set_vi_handler(7, bcm47xx_hw7_irqdispatch);

arch/mips/include/asm/setup.h

24

extern void *set_vi_handler(int n, vi_handler_t addr);

arch/mips/kernel/traps.c

2410

set_vi_handler(i, NULL);

arch/mips/mti-malta/malta-int.c

214

set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);

arch/mips/mti-malta/malta-time.c

151

set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);

arch/mips/mti-malta/malta-time.c

168

set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);

drivers/irqchip/irq-mips-cpu.c

165

set_vi_handler(hw, plat_irq_dispatch);

drivers/irqchip/irq-mips-gic.c

962

set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,