arch/microblaze/include/asm/cacheflush.h

49

extern struct scache *mbc;

arch/microblaze/kernel/cpu/cache.c

509

struct scache *mbc;

arch/microblaze/kernel/cpu/cache.c

512

static const struct scache wb_msr = {

arch/microblaze/kernel/cpu/cache.c

528

static const struct scache wb_nomsr = {

arch/microblaze/kernel/cpu/cache.c

544

static const struct scache wt_msr = {

arch/microblaze/kernel/cpu/cache.c

559

static const struct scache wt_nomsr = {

arch/microblaze/kernel/cpu/cache.c

575

static const struct scache wt_msr_noirq = {

arch/microblaze/kernel/cpu/cache.c

590

static const struct scache wt_nomsr_noirq = {

arch/microblaze/kernel/cpu/cache.c

614

mbc = (struct scache *)&wb_msr;

arch/microblaze/kernel/cpu/cache.c

622

mbc = (struct scache *)&wt_msr_noirq;

arch/microblaze/kernel/cpu/cache.c

625

mbc = (struct scache *)&wt_msr;

arch/microblaze/kernel/cpu/cache.c

631

mbc = (struct scache *)&wb_nomsr;

arch/microblaze/kernel/cpu/cache.c

639

mbc = (struct scache *)&wt_nomsr_noirq;

arch/microblaze/kernel/cpu/cache.c

642

mbc = (struct scache *)&wt_nomsr;

arch/mips/include/asm/cpu-features.h

513

#define cpu_scache_line_size() cpu_data[0].scache.linesz

arch/mips/include/asm/cpu-info.h

78

struct cache_desc scache; /* Secondary cache */

arch/mips/include/asm/r4kcache.h

246

__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )

arch/mips/include/asm/r4kcache.h

250

__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )

arch/mips/include/asm/r4kcache.h

253

__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )

arch/mips/include/asm/r4kcache.h

256

__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )

arch/mips/include/asm/r4kcache.h

260

__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )

arch/mips/include/asm/r4kcache.h

261

__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )

arch/mips/include/asm/r4kcache.h

262

__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )

arch/mips/include/asm/r4kcache.h

263

__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )

arch/mips/include/asm/r4kcache.h

306

__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )

arch/mips/include/asm/r4kcache.h

311

__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )

arch/mips/include/asm/r4kcache.h

314

__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )

arch/mips/include/asm/r4kcache.h

333

__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)

arch/mips/include/asm/r4kcache.h

334

__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)

arch/mips/include/asm/r4kcache.h

335

__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)

arch/mips/include/asm/r4kcache.h

336

__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)

arch/mips/kernel/cacheinfo.c

103

if (c->scache.waysize) {

arch/mips/kernel/cacheinfo.c

106

populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED);

arch/mips/kernel/cacheinfo.c

43

if (c->scache.waysize) {

arch/mips/kernel/cpu-probe.c

1543

c->scache.ways = 8;

arch/mips/kernel/cpu-probe.c

501

c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

arch/mips/kernel/cpu-probe.c

732

c->scache.flags = MIPS_CACHE_NOT_PRESENT;

arch/mips/mm/c-r4k.c

1434

c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);

arch/mips/mm/c-r4k.c

1435

c->scache.ways = 1;

arch/mips/mm/c-r4k.c

1436

c->scache.waybit = 0; /* does not matter */

arch/mips/mm/c-r4k.c

1446

c->scache.linesz = 32;

arch/mips/mm/c-r4k.c

1447

c->scache.ways = 4;

arch/mips/mm/c-r4k.c

1448

c->scache.waybit = 0;

arch/mips/mm/c-r4k.c

1449

c->scache.waysize = scache_size / (c->scache.ways);

arch/mips/mm/c-r4k.c

1450

c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);

arch/mips/mm/c-r4k.c

1452

scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);

arch/mips/mm/c-r4k.c

1465

c->scache.linesz = 2 << lsize;

arch/mips/mm/c-r4k.c

1467

c->scache.linesz = 0;

arch/mips/mm/c-r4k.c

1468

c->scache.sets = 64 << ((config2 >> 8) & 15);

arch/mips/mm/c-r4k.c

1469

c->scache.ways = 1 + (config2 & 15);

arch/mips/mm/c-r4k.c

1473

c->scache.sets *= 2;

arch/mips/mm/c-r4k.c

1475

c->scache.sets *= 4;

arch/mips/mm/c-r4k.c

1477

scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;

arch/mips/mm/c-r4k.c

1479

c->scache.waybit = 0;

arch/mips/mm/c-r4k.c

1480

c->scache.waysize = scache_size / c->scache.ways;

arch/mips/mm/c-r4k.c

1482

scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);

arch/mips/mm/c-r4k.c

1514

c->scache.linesz = 64 << ((config >> 13) & 1);

arch/mips/mm/c-r4k.c

1515

c->scache.ways = 2;

arch/mips/mm/c-r4k.c

1516

c->scache.waybit= 0;

arch/mips/mm/c-r4k.c

1552

scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;

arch/mips/mm/c-r4k.c

1555

way_string[c->scache.ways], c->scache.linesz);

arch/mips/mm/c-r4k.c

1562

if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))

arch/mips/mm/c-r4k.c

1574

c->scache.waysize = scache_size / c->scache.ways;

arch/mips/mm/c-r4k.c

1576

c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);

arch/mips/mm/c-r4k.c

1579

scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);

arch/mips/mm/c-r4k.c

1776

if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)

arch/mips/mm/sc-mips.c

143

c->scache.linesz = 2 << tmp;

arch/mips/mm/sc-mips.c

161

c->scache.sets = 64 << sets;

arch/mips/mm/sc-mips.c

166

c->scache.linesz = 2 << line_sz;

arch/mips/mm/sc-mips.c

170

c->scache.ways = assoc + 1;

arch/mips/mm/sc-mips.c

171

c->scache.waysize = c->scache.sets * c->scache.linesz;

arch/mips/mm/sc-mips.c

172

c->scache.waybit = __ffs(c->scache.waysize);

arch/mips/mm/sc-mips.c

174

if (c->scache.linesz) {

arch/mips/mm/sc-mips.c

175

c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

arch/mips/mm/sc-mips.c

190

c->scache.flags |= MIPS_CACHE_NOT_PRESENT;

arch/mips/mm/sc-mips.c

214

c->scache.sets = 64 << tmp;

arch/mips/mm/sc-mips.c

220

c->scache.ways = tmp + 1;

arch/mips/mm/sc-mips.c

232

c->scache.ways = 4;

arch/mips/mm/sc-mips.c

241

c->scache.sets = 256;

arch/mips/mm/sc-mips.c

242

c->scache.ways = 4;

arch/mips/mm/sc-mips.c

247

c->scache.waysize = c->scache.sets * c->scache.linesz;

arch/mips/mm/sc-mips.c

248

c->scache.waybit = __ffs(c->scache.waysize);

arch/mips/mm/sc-mips.c

250

c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

arch/mips/mm/sc-rm7k.c

237

c->scache.linesz = sc_lsize;

arch/mips/mm/sc-rm7k.c

238

c->scache.ways = 4;

arch/mips/mm/sc-rm7k.c

239

c->scache.waybit= __ffs(scache_size / c->scache.ways);

arch/mips/mm/sc-rm7k.c

240

c->scache.waysize = scache_size / c->scache.ways;

arch/mips/mm/sc-rm7k.c

241

c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);

arch/sh/include/asm/processor.h

79

struct cache_info scache; /* Secondary cache */

arch/sh/kernel/cpu/init.c

212

l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache);

arch/sh/kernel/cpu/proc.c

122

show_cacheinfo(m, "scache", c->scache);

arch/sh/kernel/cpu/sh4/probe.c

242

boot_cpu_data.scache.way_incr = (1 << 16);

arch/sh/kernel/cpu/sh4/probe.c

243

boot_cpu_data.scache.entry_shift = 5;

arch/sh/kernel/cpu/sh4/probe.c

244

boot_cpu_data.scache.ways = 4;

arch/sh/kernel/cpu/sh4/probe.c

245

boot_cpu_data.scache.linesz = L1_CACHE_BYTES;

arch/sh/kernel/cpu/sh4/probe.c

247

boot_cpu_data.scache.entry_mask =

arch/sh/kernel/cpu/sh4/probe.c

248

(boot_cpu_data.scache.way_incr -

arch/sh/kernel/cpu/sh4/probe.c

249

boot_cpu_data.scache.linesz);

arch/sh/kernel/cpu/sh4/probe.c

251

boot_cpu_data.scache.sets = size /

arch/sh/kernel/cpu/sh4/probe.c

252

(boot_cpu_data.scache.linesz *

arch/sh/kernel/cpu/sh4/probe.c

253

boot_cpu_data.scache.ways);

arch/sh/kernel/cpu/sh4/probe.c

255

boot_cpu_data.scache.way_size =

arch/sh/kernel/cpu/sh4/probe.c

256

(boot_cpu_data.scache.sets *

arch/sh/kernel/cpu/sh4/probe.c

257

boot_cpu_data.scache.linesz);

arch/sh/mm/cache.c

289

boot_cpu_data.scache.ways,

arch/sh/mm/cache.c

290

boot_cpu_data.scache.sets,

arch/sh/mm/cache.c

291

boot_cpu_data.scache.way_incr);

arch/sh/mm/cache.c

293

boot_cpu_data.scache.entry_mask,

arch/sh/mm/cache.c

294

boot_cpu_data.scache.alias_mask,

arch/sh/mm/cache.c

295

boot_cpu_data.scache.n_aliases);

arch/sh/mm/cache.c

309

compute_alias(&boot_cpu_data.scache);