Symbol: set_rate
arch/arm/mach-omap1/clock.c
730
if (clk->set_rate)
arch/arm/mach-omap1/clock.c
731
ret = clk->set_rate(clk, rate, p_rate);
arch/arm/mach-omap1/clock.c
782
.set_rate = omap1_clk_set_rate,
arch/arm/mach-omap1/clock.c
795
.set_rate = omap1_clk_set_rate,
arch/arm/mach-omap1/clock.h
83
int (*set_rate)(struct omap1_clk *clk, unsigned long rate,
arch/arm/mach-omap1/clock_data.c
113
.set_rate = &omap1_set_sossi_rate,
arch/arm/mach-omap1/clock_data.c
121
.set_rate = omap1_clk_set_rate_ckctl_arm,
arch/arm/mach-omap1/clock_data.c
135
.set_rate = omap1_clk_set_rate_ckctl_arm,
arch/arm/mach-omap1/clock_data.c
205
.set_rate = omap1_clk_set_rate_ckctl_arm,
arch/arm/mach-omap1/clock_data.c
213
.set_rate = omap1_clk_set_rate_ckctl_arm,
arch/arm/mach-omap1/clock_data.c
224
.set_rate = &omap1_clk_set_rate_dsp_domain,
arch/arm/mach-omap1/clock_data.c
248
.set_rate = omap1_clk_set_rate_ckctl_arm,
arch/arm/mach-omap1/clock_data.c
340
.set_rate = omap1_clk_set_rate_ckctl_arm,
arch/arm/mach-omap1/clock_data.c
353
.set_rate = omap1_clk_set_rate_ckctl_arm,
arch/arm/mach-omap1/clock_data.c
372
.set_rate = &omap1_set_uart_rate,
arch/arm/mach-omap1/clock_data.c
408
.set_rate = &omap1_set_uart_rate,
arch/arm/mach-omap1/clock_data.c
425
.set_rate = &omap1_set_uart_rate,
arch/arm/mach-omap1/clock_data.c
521
.set_rate = &omap1_set_ext_clk_rate,
arch/arm/mach-omap1/clock_data.c
538
.set_rate = &omap1_set_ext_clk_rate,
arch/arm/mach-omap1/clock_data.c
581
.set_rate = &omap1_select_table_rate,
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
219
.set_rate = &omap2_select_table_rate,
arch/arm/mach-versatile/spc.c
520
.set_rate = spc_set_rate,
arch/mips/alchemy/common/clock.c
240
.set_rate = alchemy_clk_aux_setr,
arch/mips/alchemy/common/clock.c
593
.set_rate = alchemy_clk_fgv1_setr,
arch/mips/alchemy/common/clock.c
734
.set_rate = alchemy_clk_fgv2_setr,
arch/mips/alchemy/common/clock.c
942
.set_rate = alchemy_clk_csrc_setr,
drivers/clk/actions/owl-composite.c
164
.set_rate = owl_comp_div_set_rate,
drivers/clk/actions/owl-composite.c
181
.set_rate = owl_comp_fact_set_rate,
drivers/clk/actions/owl-composite.c
193
.set_rate = owl_comp_fix_fact_set_rate,
drivers/clk/actions/owl-divider.c
83
.set_rate = owl_divider_set_rate,
drivers/clk/actions/owl-factor.c
221
.set_rate = owl_factor_set_rate,
drivers/clk/actions/owl-pll.c
200
.set_rate = owl_pll_set_rate,
drivers/clk/at91/clk-audio-pll.c
436
.set_rate = clk_audio_pll_frac_set_rate,
drivers/clk/at91/clk-audio-pll.c
444
.set_rate = clk_audio_pll_pad_set_rate,
drivers/clk/at91/clk-audio-pll.c
452
.set_rate = clk_audio_pll_pmc_set_rate,
drivers/clk/at91/clk-generated.c
289
.set_rate = clk_generated_set_rate,
drivers/clk/at91/clk-h32mx.c
92
.set_rate = clk_sama5d4_h32mx_set_rate,
drivers/clk/at91/clk-master.c
807
.set_rate = clk_sama7g5_master_set_rate,
drivers/clk/at91/clk-peripheral.c
442
.set_rate = clk_sam9x5_peripheral_set_rate,
drivers/clk/at91/clk-peripheral.c
453
.set_rate = clk_sam9x5_peripheral_set_rate,
drivers/clk/at91/clk-pll.c
308
.set_rate = clk_pll_set_rate,
drivers/clk/at91/clk-plldiv.c
82
.set_rate = clk_plldiv_set_rate,
drivers/clk/at91/clk-programmable.c
210
.set_rate = clk_programmable_set_rate,
drivers/clk/at91/clk-sam9x60-pll.c
326
.set_rate = sam9x60_frac_pll_set_rate,
drivers/clk/at91/clk-sam9x60-pll.c
337
.set_rate = sam9x60_frac_pll_set_rate_chg,
drivers/clk/at91/clk-sam9x60-pll.c
612
.set_rate = sam9x60_div_pll_set_rate,
drivers/clk/at91/clk-sam9x60-pll.c
623
.set_rate = sam9x60_div_pll_set_rate_chg,
drivers/clk/at91/clk-smd.c
109
.set_rate = at91sam9x5_clk_smd_set_rate,
drivers/clk/at91/clk-usb.c
181
.set_rate = at91sam9x5_clk_usb_set_rate,
drivers/clk/at91/clk-usb.c
219
.set_rate = at91sam9x5_clk_usb_set_rate,
drivers/clk/at91/clk-usb.c
390
.set_rate = at91rm9200_clk_usb_set_rate,
drivers/clk/axs10x/i2s_pll_clock.c
160
.set_rate = i2s_pll_set_rate,
drivers/clk/axs10x/pll_clock.c
214
.set_rate = axs10x_pll_set_rate,
drivers/clk/baikal-t1/ccu-div.c
543
.set_rate = ccu_div_var_set_rate_fast,
drivers/clk/baikal-t1/ccu-div.c
550
.set_rate = ccu_div_var_set_rate_slow,
drivers/clk/baikal-t1/ccu-div.c
560
.set_rate = ccu_div_fixed_set_rate,
drivers/clk/baikal-t1/ccu-div.c
574
.set_rate = ccu_div_fixed_set_rate,
drivers/clk/baikal-t1/ccu-pll.c
487
.set_rate = ccu_pll_set_rate_norst,
drivers/clk/baikal-t1/ccu-pll.c
497
.set_rate = ccu_pll_set_rate_reset,
drivers/clk/bcm/clk-bcm2835.c
1317
.set_rate = bcm2835_clock_set_rate,
drivers/clk/bcm/clk-bcm2835.c
1336
.set_rate = bcm2835_clock_set_rate,
drivers/clk/bcm/clk-bcm2835.c
790
.set_rate = bcm2835_pll_set_rate,
drivers/clk/bcm/clk-bcm2835.c
910
.set_rate = bcm2835_pll_divider_set_rate,
drivers/clk/bcm/clk-iproc-asiu.c
177
.set_rate = iproc_asiu_clk_set_rate,
drivers/clk/bcm/clk-iproc-pll.c
572
.set_rate = iproc_pll_set_rate,
drivers/clk/bcm/clk-iproc-pll.c
694
.set_rate = iproc_clk_set_rate,
drivers/clk/bcm/clk-kona.c
1165
.set_rate = kona_peri_clk_set_rate,
drivers/clk/bcm/clk-raspberrypi.c
327
.set_rate = raspberrypi_fw_set_rate,
drivers/clk/clk-apple-nco.c
249
.set_rate = applnco_set_rate,
drivers/clk/clk-axi-clkgen.c
557
.set_rate = axi_clkgen_set_rate,
drivers/clk/clk-bm1880.c
667
.set_rate = bm1880_clk_div_set_rate,
drivers/clk/clk-cdce706.c
257
.set_rate = cdce706_pll_set_rate,
drivers/clk/clk-cdce706.c
383
.set_rate = cdce706_divider_set_rate,
drivers/clk/clk-cdce706.c
449
.set_rate = cdce706_clkout_set_rate,
drivers/clk/clk-cdce925.c
272
.set_rate = cdce925_pll_set_rate,
drivers/clk/clk-cdce925.c
460
.set_rate = cdce925_clk_set_rate,
drivers/clk/clk-cdce925.c
510
.set_rate = cdce925_clk_y1_set_rate,
drivers/clk/clk-composite.c
174
return rate_ops->set_rate(rate_hw, rate, parent_rate);
drivers/clk/clk-composite.c
194
rate_ops->set_rate(rate_hw, rate, parent_rate);
drivers/clk/clk-composite.c
198
rate_ops->set_rate(rate_hw, rate, parent_rate);
drivers/clk/clk-composite.c
296
if (rate_ops->set_rate) {
drivers/clk/clk-composite.c
298
clk_composite_ops->set_rate =
drivers/clk/clk-composite.c
310
if (mux_ops->set_parent && rate_ops->set_rate)
drivers/clk/clk-cs2000-cp.c
438
.set_rate = cs2000_set_rate,
drivers/clk/clk-divider.c
510
.set_rate = clk_divider_set_rate,
drivers/clk/clk-ep93xx.c
350
.set_rate = ep93xx_ddiv_set_rate,
drivers/clk/clk-ep93xx.c
443
.set_rate = ep93xx_div_set_rate,
drivers/clk/clk-fixed-factor.c
75
.set_rate = clk_factor_set_rate,
drivers/clk/clk-fractional-divider.c
261
.set_rate = clk_fd_set_rate,
drivers/clk/clk-gemini.c
186
.set_rate = gemini_pci_set_rate,
drivers/clk/clk-highbank.c
191
.set_rate = clk_pll_set_rate,
drivers/clk/clk-highbank.c
263
.set_rate = clk_periclk_set_rate,
drivers/clk/clk-hsdk-pll.c
302
.set_rate = hsdk_pll_set_rate,
drivers/clk/clk-lan966x.c
199
.set_rate = lan966x_gck_set_rate,
drivers/clk/clk-lmk04832.c
1171
.set_rate = lmk04832_dclk_set_rate,
drivers/clk/clk-lmk04832.c
588
.set_rate = lmk04832_vco_set_rate,
drivers/clk/clk-lmk04832.c
956
.set_rate = lmk04832_sclk_set_rate,
drivers/clk/clk-loongson1.c
149
.set_rate = ls1x_divider_set_rate,
drivers/clk/clk-max9485.c
230
.set_rate = max9485_clkout_set_rate,
drivers/clk/clk-milbeaut.c
453
.set_rate = m10v_clk_divider_set_rate,
drivers/clk/clk-multiplier.c
156
.set_rate = clk_multiplier_set_rate,
drivers/clk/clk-plldig.c
181
.set_rate = plldig_set_rate,
drivers/clk/clk-rp1.c
1187
.set_rate = rp1_pll_core_set_rate,
drivers/clk/clk-rp1.c
1193
.set_rate = rp1_pll_set_rate,
drivers/clk/clk-rp1.c
1210
.set_rate = rp1_pll_divider_set_rate,
drivers/clk/clk-rp1.c
1223
.set_rate = rp1_clock_set_rate,
drivers/clk/clk-rp1.c
1228
.set_rate = rp1_varsrc_set_rate,
drivers/clk/clk-rpmi.c
440
.set_rate = rpmi_clk_set_rate,
drivers/clk/clk-scmi.c
303
ops->set_rate = scmi_clk_set_rate;
drivers/clk/clk-scpi.c
130
.set_rate = scpi_dvfs_set_rate,
drivers/clk/clk-scpi.c
58
.set_rate = scpi_clk_set_rate,
drivers/clk/clk-si514.c
301
.set_rate = si514_set_rate,
drivers/clk/clk-si521xx.c
214
.set_rate = si521xx_diff_set_rate,
drivers/clk/clk-si5341.c
751
.set_rate = si5341_synth_clk_set_rate,
drivers/clk/clk-si5341.c
940
.set_rate = si5341_output_clk_set_rate,
drivers/clk/clk-si5351.c
1156
.set_rate = si5351_clkout_set_rate,
drivers/clk/clk-si5351.c
336
.set_rate = si5351_vxco_set_rate,
drivers/clk/clk-si5351.c
542
.set_rate = si5351_pll_set_rate,
drivers/clk/clk-si5351.c
801
.set_rate = si5351_msynth_set_rate,
drivers/clk/clk-si544.c
412
.set_rate = si544_set_rate,
drivers/clk/clk-si570.c
378
.set_rate = si570_set_rate,
drivers/clk/clk-sp7021.c
536
.set_rate = sp_pll_set_rate
drivers/clk/clk-sparx5.c
229
.set_rate = s5_pll_set_rate,
drivers/clk/clk-stm32f4.c
480
.set_rate = clk_apb_mul_set_rate,
drivers/clk/clk-stm32f4.c
757
.set_rate = stm32f4_pll_set_rate,
drivers/clk/clk-stm32f4.c
792
ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
drivers/clk/clk-stm32f4.c
803
.set_rate = stm32f4_pll_div_set_rate,
drivers/clk/clk-stm32h7.c
867
ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
drivers/clk/clk-stm32h7.c
878
.set_rate = odf_divider_set_rate,
drivers/clk/clk-tps68470.c
192
.set_rate = tps68470_clk_set_rate,
drivers/clk/clk-versaclock3.c
363
.set_rate = vc3_pfd_set_rate,
drivers/clk/clk-versaclock3.c
452
.set_rate = vc3_pll_set_rate,
drivers/clk/clk-versaclock3.c
547
.set_rate = vc3_div_set_rate,
drivers/clk/clk-versaclock5.c
336
.set_rate = vc5_dbl_set_rate,
drivers/clk/clk-versaclock5.c
429
.set_rate = vc5_pfd_set_rate,
drivers/clk/clk-versaclock5.c
499
.set_rate = vc5_pll_set_rate,
drivers/clk/clk-versaclock5.c
602
.set_rate = vc5_fod_set_rate,
drivers/clk/clk-versaclock7.c
1033
.set_rate = vc7_iod_set_rate,
drivers/clk/clk-versaclock7.c
959
.set_rate = vc7_fod_set_rate,
drivers/clk/clk-vt8500.c
207
.set_rate = vt8500_dclk_set_rate,
drivers/clk/clk-vt8500.c
216
.set_rate = vt8500_dclk_set_rate,
drivers/clk/clk-vt8500.c
680
.set_rate = vtwm_pll_set_rate,
drivers/clk/clk-wm831x.c
221
.set_rate = wm831x_fll_set_rate,
drivers/clk/clk-xgene.c
342
.set_rate = xgene_clk_pmd_set_rate,
drivers/clk/clk-xgene.c
627
.set_rate = xgene_clk_set_rate,
drivers/clk/clk.c
2445
if (!skip_set_rate && core->ops->set_rate)
drivers/clk/clk.c
2446
core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
drivers/clk/clk.c
3918
if (core->ops->set_rate &&
drivers/clk/clk.c
3949
!(core->ops->set_parent && core->ops->set_rate)) {
drivers/clk/clk.c
4520
.set_rate = clk_nodrv_set_rate,
drivers/clk/clk_test.c
102
.set_rate = clk_dummy_set_rate,
drivers/clk/clk_test.c
108
.set_rate = clk_dummy_set_rate,
drivers/clk/clk_test.c
114
.set_rate = clk_dummy_set_rate,
drivers/clk/clk_test.c
303
unsigned long set_rate;
drivers/clk/clk_test.c
314
set_rate = clk_get_rate(clk);
drivers/clk/clk_test.c
315
KUNIT_ASSERT_GT(test, set_rate, 0);
drivers/clk/clk_test.c
316
KUNIT_EXPECT_EQ(test, rounded_rate, set_rate);
drivers/clk/davinci/pll.c
200
.set_rate = davinci_pll_set_rate,
drivers/clk/hisilicon/clk-hi3559a.c
450
.set_rate = clk_pll_set_rate,
drivers/clk/hisilicon/clk-hi3620.c
406
.set_rate = mmc_clk_set_rate,
drivers/clk/hisilicon/clk-hi3660-stub.c
101
.set_rate = hi3660_stub_clk_set_rate,
drivers/clk/hisilicon/clk-hi6220-stub.c
192
.set_rate = hi6220_stub_clk_set_rate,
drivers/clk/hisilicon/clkdivider-hi6220.c
97
.set_rate = hi6220_clkdiv_set_rate,
drivers/clk/imx/clk-busy.c
63
ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate);
drivers/clk/imx/clk-busy.c
73
.set_rate = clk_busy_divider_set_rate,
drivers/clk/imx/clk-composite-8m.c
141
.set_rate = imx8m_clk_composite_divider_set_rate,
drivers/clk/imx/clk-composite-93.c
139
.set_rate = imx93_clk_composite_divider_set_rate,
drivers/clk/imx/clk-cpu.c
72
.set_rate = clk_cpu_set_rate,
drivers/clk/imx/clk-divider-gate.c
163
.set_rate = clk_divider_gate_set_rate,
drivers/clk/imx/clk-fixup-div.c
85
.set_rate = clk_fixup_div_set_rate,
drivers/clk/imx/clk-frac-pll.c
204
.set_rate = clk_pll_set_rate,
drivers/clk/imx/clk-fracn-gppll.c
356
.set_rate = clk_fracn_gppll_set_rate,
drivers/clk/imx/clk-pfd.c
123
.set_rate = clk_pfd_set_rate,
drivers/clk/imx/clk-pfdv2.c
199
.set_rate = clk_pfdv2_set_rate,
drivers/clk/imx/clk-pll14xx.c
481
.set_rate = clk_pll1416x_set_rate,
drivers/clk/imx/clk-pll14xx.c
494
.set_rate = clk_pll1443x_set_rate,
drivers/clk/imx/clk-pllv2.c
246
.set_rate = clk_pllv2_set_rate,
drivers/clk/imx/clk-pllv3.c
157
.set_rate = clk_pllv3_set_rate,
drivers/clk/imx/clk-pllv3.c
214
.set_rate = clk_pllv3_sys_set_rate,
drivers/clk/imx/clk-pllv3.c
305
.set_rate = clk_pllv3_av_set_rate,
drivers/clk/imx/clk-pllv3.c
401
.set_rate = clk_pllv3_vf610_set_rate,
drivers/clk/imx/clk-pllv4.c
240
.set_rate = clk_pllv4_set_rate,
drivers/clk/imx/clk-scu.c
440
.set_rate = clk_scu_set_rate,
drivers/clk/imx/clk-scu.c
450
.set_rate = clk_scu_atf_set_cpu_rate,
drivers/clk/imx/clk-scu.c
458
.set_rate = clk_scu_set_rate,
drivers/clk/imx/clk-scu.c
787
.set_rate = clk_gpr_div_scu_set_rate,
drivers/clk/imx/clk-sscg-pll.c
494
.set_rate = clk_sscg_pll_set_rate,
drivers/clk/ingenic/cgu.c
323
.set_rate = ingenic_pll_set_rate,
drivers/clk/ingenic/cgu.c
633
.set_rate = ingenic_clk_set_rate,
drivers/clk/ingenic/jz4780-cgu.c
216
.set_rate = jz4780_otg_phy_set_rate,
drivers/clk/ingenic/tcu.c
226
.set_rate = ingenic_tcu_set_rate,
drivers/clk/ingenic/x1000-cgu.c
166
.set_rate = x1000_otg_phy_set_rate,
drivers/clk/keystone/sci-clk.c
269
.set_rate = sci_clk_set_rate,
drivers/clk/mediatek/clk-pll.c
313
.set_rate = mtk_pll_set_rate,
drivers/clk/mediatek/clk-pll.c
322
.set_rate = mtk_pll_set_rate,
drivers/clk/mediatek/clk-pllfh.c
47
.set_rate = mtk_fhctl_set_rate,
drivers/clk/meson/clk-cpu-dyndiv.c
67
.set_rate = meson_clk_cpu_dyndiv_set_rate,
drivers/clk/meson/clk-dualdiv.c
132
.set_rate = meson_clk_dualdiv_set_rate,
drivers/clk/meson/clk-mpll.c
168
.set_rate = mpll_set_rate,
drivers/clk/meson/clk-pll.c
489
.set_rate = meson_clk_pll_set_rate,
drivers/clk/meson/clk-regmap.c
172
.set_rate = clk_regmap_div_set_rate,
drivers/clk/meson/sclk-div.c
247
.set_rate = sclk_div_set_rate,
drivers/clk/meson/vclk.c
134
.set_rate = meson_vclk_div_set_rate,
drivers/clk/microchip/clk-core.c
212
.set_rate = pbclk_set_rate,
drivers/clk/microchip/clk-core.c
549
.set_rate = roclk_set_rate,
drivers/clk/microchip/clk-core.c
727
.set_rate = spll_clk_set_rate,
drivers/clk/microchip/clk-core.c
904
.set_rate = sclk_set_rate,
drivers/clk/microchip/clk-mpfs.c
296
.set_rate = mpfs_cfg_clk_set_rate,
drivers/clk/mmp/clk-audio.c
234
.set_rate = audio_pll_set_rate,
drivers/clk/mmp/clk-frac.c
165
.set_rate = clk_factor_set_rate,
drivers/clk/mmp/clk-mix.c
432
.set_rate = mmp_clk_set_rate,
drivers/clk/mstar/clk-msc313-cpupll.c
174
.set_rate = msc313_cpupll_set_rate,
drivers/clk/mvebu/ap-cpu-clk.c
228
.set_rate = ap_cpu_clk_set_rate,
drivers/clk/mvebu/armada-37xx-periph.c
607
.set_rate = clk_pm_cpu_set_rate,
drivers/clk/mvebu/clk-corediv.c
205
.set_rate = clk_corediv_set_rate,
drivers/clk/mvebu/clk-corediv.c
221
.set_rate = clk_corediv_set_rate,
drivers/clk/mvebu/clk-corediv.c
234
.set_rate = clk_corediv_set_rate,
drivers/clk/mvebu/clk-corediv.c
246
.set_rate = clk_corediv_set_rate,
drivers/clk/mvebu/clk-cpu.c
165
.set_rate = clk_cpu_set_rate,
drivers/clk/mvebu/dove-divider.c
156
.set_rate = dove_set_clock,
drivers/clk/mxs/clk-div.c
57
ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
drivers/clk/mxs/clk-div.c
67
.set_rate = clk_div_set_rate,
drivers/clk/mxs/clk-frac.c
109
.set_rate = clk_frac_set_rate,
drivers/clk/mxs/clk-ref.c
110
.set_rate = clk_ref_set_rate,
drivers/clk/nuvoton/clk-ma35d1-divider.c
76
.set_rate = ma35d1_clkdiv_set_rate,
drivers/clk/nuvoton/clk-ma35d1-pll.c
320
.set_rate = ma35d1_clk_pll_set_rate,
drivers/clk/nxp/clk-lpc18xx-cgu.c
449
.set_rate = lpc18xx_pll0_set_rate,
drivers/clk/nxp/clk-lpc32xx.c
705
.set_rate = _sr, \
drivers/clk/nxp/clk-lpc32xx.c
999
.set_rate = clk_divider_set_rate,
drivers/clk/pistachio/clk-pll.c
308
.set_rate = pll_gf40lp_frac_set_rate,
drivers/clk/pistachio/clk-pll.c
440
.set_rate = pll_gf40lp_laint_set_rate,
drivers/clk/pxa/clk-pxa.h
58
.set_rate = name ## _set_rate, \
drivers/clk/qcom/clk-alpha-pll.c
1198
.set_rate = clk_alpha_pll_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1208
.set_rate = alpha_pll_huayra_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1218
.set_rate = clk_alpha_pll_hwfsm_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1315
.set_rate = clk_alpha_pll_postdiv_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1563
.set_rate = alpha_pll_fabia_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1658
.set_rate = clk_trion_pll_postdiv_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1704
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1856
.set_rate = alpha_pll_trion_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1867
.set_rate = alpha_pll_trion_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1874
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
1926
.set_rate = clk_alpha_pll_agera_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
2142
.set_rate = alpha_pll_lucid_5lpe_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
2158
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
2327
.set_rate = clk_zonda_pll_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
2562
.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
2573
.set_rate = alpha_pll_lucid_5lpe_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
2584
.set_rate = alpha_pll_lucid_5lpe_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
2898
.set_rate = clk_alpha_pll_stromer_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
2964
.set_rate = clk_alpha_pll_stromer_plus_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
2994
.set_rate = clk_zonda_pll_set_rate,
drivers/clk/qcom/clk-alpha-pll.c
3200
.set_rate = clk_alpha_pll_slew_set_rate,
drivers/clk/qcom/clk-hfpll.c
249
.set_rate = clk_hfpll_set_rate,
drivers/clk/qcom/clk-krait.c
146
.set_rate = krait_div2_set_rate,
drivers/clk/qcom/clk-pll.c
175
.set_rate = clk_pll_set_rate,
drivers/clk/qcom/clk-pll.c
332
.set_rate = clk_pll_sr2_set_rate,
drivers/clk/qcom/clk-rcg.c
829
.set_rate = clk_rcg_set_rate,
drivers/clk/qcom/clk-rcg.c
840
.set_rate = clk_rcg_set_floor_rate,
drivers/clk/qcom/clk-rcg.c
851
.set_rate = clk_rcg_bypass_set_rate,
drivers/clk/qcom/clk-rcg.c
862
.set_rate = clk_rcg_bypass2_set_rate,
drivers/clk/qcom/clk-rcg.c
874
.set_rate = clk_rcg_pixel_set_rate,
drivers/clk/qcom/clk-rcg.c
886
.set_rate = clk_rcg_esc_set_rate,
drivers/clk/qcom/clk-rcg.c
898
.set_rate = clk_rcg_lcc_set_rate,
drivers/clk/qcom/clk-rcg.c
910
.set_rate = clk_dyn_rcg_set_rate,
drivers/clk/qcom/clk-rcg2.c
1038
.set_rate = clk_byte_set_rate,
drivers/clk/qcom/clk-rcg2.c
1108
.set_rate = clk_byte2_set_rate,
drivers/clk/qcom/clk-rcg2.c
1199
.set_rate = clk_pixel_set_rate,
drivers/clk/qcom/clk-rcg2.c
1314
.set_rate = clk_gfx3d_set_rate,
drivers/clk/qcom/clk-rcg2.c
1551
.set_rate = clk_rcg2_shared_set_rate,
drivers/clk/qcom/clk-rcg2.c
1563
.set_rate = clk_rcg2_shared_set_floor_rate,
drivers/clk/qcom/clk-rcg2.c
1593
.set_rate = clk_rcg2_shared_set_rate,
drivers/clk/qcom/clk-rcg2.c
1855
.set_rate = clk_rcg2_dp_set_rate,
drivers/clk/qcom/clk-rcg2.c
807
.set_rate = clk_rcg2_set_rate,
drivers/clk/qcom/clk-rcg2.c
820
.set_rate = clk_rcg2_set_gp_rate,
drivers/clk/qcom/clk-rcg2.c
832
.set_rate = clk_rcg2_set_floor_rate,
drivers/clk/qcom/clk-rcg2.c
845
.set_rate = clk_rcg2_fm_set_rate,
drivers/clk/qcom/clk-rcg2.c
980
.set_rate = clk_edp_pixel_set_rate,
drivers/clk/qcom/clk-regmap-divider.c
73
.set_rate = div_set_rate,
drivers/clk/qcom/clk-regmap-mux-div.c
226
.set_rate = mux_div_set_rate,
drivers/clk/qcom/clk-rpm.c
393
.set_rate = clk_rpm_set_rate,
drivers/clk/qcom/clk-rpmh.c
341
.set_rate = clk_rpmh_bcm_set_rate,
drivers/clk/qcom/clk-smd-rpm.c
429
.set_rate = clk_smd_rpm_set_rate,
drivers/clk/qcom/clk-spmi-pmic-div.c
172
.set_rate = clk_spmi_pmic_div_set_rate,
drivers/clk/qcom/gcc-ipq4019.c
211
.set_rate = clk_cpu_div_set_rate,
drivers/clk/qcom/ipq-cmn-pll.c
284
.set_rate = clk_cmn_pll_set_rate,
drivers/clk/renesas/clk-div6.c
207
.set_rate = cpg_div6_clock_set_rate,
drivers/clk/renesas/r9a06g032-clocks.c
1053
.set_rate = r9a06g032_div_set_rate,
drivers/clk/renesas/rcar-gen2-cpg.c
133
.set_rate = cpg_z_clk_set_rate,
drivers/clk/renesas/rcar-gen3-cpg.c
111
.set_rate = cpg_pll_clk_set_rate,
drivers/clk/renesas/rcar-gen3-cpg.c
259
.set_rate = cpg_z_clk_set_rate,
drivers/clk/renesas/rcar-gen4-cpg.c
193
.set_rate = cpg_pll_8_25_clk_set_rate,
drivers/clk/renesas/rcar-gen4-cpg.c
364
.set_rate = cpg_z_clk_set_rate,
drivers/clk/renesas/rzg2l-cpg.c
1019
.set_rate = rzg2l_cpg_sipll5_set_rate,
drivers/clk/renesas/rzg2l-cpg.c
373
.set_rate = rzg3s_div_clk_set_rate,
drivers/clk/renesas/rzg2l-cpg.c
789
.set_rate = rzg2l_cpg_dsi_div_set_rate,
drivers/clk/renesas/rzv2h-cpg.c
517
.set_rate = rzv2h_cpg_plldsi_div_set_rate,
drivers/clk/renesas/rzv2h-cpg.c
725
.set_rate = rzv2h_cpg_plldsi_set_rate,
drivers/clk/renesas/rzv2h-cpg.c
846
.set_rate = rzv2h_ddiv_set_rate,
drivers/clk/rockchip/clk-ddr.c
86
.set_rate = rockchip_ddrclk_sip_set_rate,
drivers/clk/rockchip/clk-half-divider.c
147
.set_rate = clk_half_divider_set_rate,
drivers/clk/rockchip/clk-pll.c
1045
.set_rate = rockchip_rk3588_pll_set_rate,
drivers/clk/rockchip/clk-pll.c
361
.set_rate = rockchip_rk3036_pll_set_rate,
drivers/clk/rockchip/clk-pll.c
580
.set_rate = rockchip_rk3066_pll_set_rate,
drivers/clk/rockchip/clk-pll.c
845
.set_rate = rockchip_rk3399_pll_set_rate,
drivers/clk/samsung/clk-acpm.c
92
return clk->handle->ops.dvfs_ops.set_rate(clk->handle,
drivers/clk/samsung/clk-acpm.c
99
.set_rate = acpm_clk_set_rate,
drivers/clk/samsung/clk-pll.c
1081
.set_rate = samsung_pll2550xx_set_rate,
drivers/clk/samsung/clk-pll.c
1173
.set_rate = samsung_pll2650x_set_rate,
drivers/clk/samsung/clk-pll.c
1263
.set_rate = samsung_pll2650xx_set_rate,
drivers/clk/samsung/clk-pll.c
1424
.set_rate = samsung_pll1031x_set_rate,
drivers/clk/samsung/clk-pll.c
286
.set_rate = samsung_pll35xx_set_rate,
drivers/clk/samsung/clk-pll.c
397
.set_rate = samsung_pll36xx_set_rate,
drivers/clk/samsung/clk-pll.c
502
.set_rate = samsung_pll0822x_set_rate,
drivers/clk/samsung/clk-pll.c
598
.set_rate = samsung_pll0831x_set_rate,
drivers/clk/samsung/clk-pll.c
723
.set_rate = samsung_pll45xx_set_rate,
drivers/clk/samsung/clk-pll.c
868
.set_rate = samsung_pll46xx_set_rate,
drivers/clk/sifive/fu540-prci.h
51
.set_rate = sifive_prci_wrpll_set_rate,
drivers/clk/sifive/fu740-prci.h
57
.set_rate = sifive_prci_wrpll_set_rate,
drivers/clk/sophgo/clk-cv18xx-ip.c
299
.set_rate = div_set_rate,
drivers/clk/sophgo/clk-cv18xx-ip.c
392
.set_rate = bypass_div_set_rate,
drivers/clk/sophgo/clk-cv18xx-ip.c
509
.set_rate = mux_set_rate,
drivers/clk/sophgo/clk-cv18xx-ip.c
605
.set_rate = bypass_mux_set_rate,
drivers/clk/sophgo/clk-cv18xx-ip.c
69
.set_rate = gate_set_rate,
drivers/clk/sophgo/clk-cv18xx-ip.c
796
.set_rate = mmux_set_rate,
drivers/clk/sophgo/clk-cv18xx-ip.c
904
.set_rate = aclk_set_rate,
drivers/clk/sophgo/clk-cv18xx-pll.c
185
.set_rate = ipll_set_rate,
drivers/clk/sophgo/clk-cv18xx-pll.c
415
.set_rate = fpll_set_rate,
drivers/clk/sophgo/clk-sg2042-clkgen.c
258
.set_rate = sg2042_clk_divider_set_rate,
drivers/clk/sophgo/clk-sg2042-pll.c
414
.set_rate = sg2042_clk_pll_set_rate,
drivers/clk/sophgo/clk-sg2044-pll.c
378
.set_rate = sg2044_pll_set_rate,
drivers/clk/sophgo/clk-sg2044.c
234
.set_rate = sg2044_div_set_rate,
drivers/clk/sophgo/clk-sg2044.c
240
.set_rate = sg2044_div_set_rate,
drivers/clk/spacemit/ccu_ddn.c
85
.set_rate = ccu_ddn_set_rate,
drivers/clk/spacemit/ccu_mix.c
210
.set_rate = ccu_factor_set_rate,
drivers/clk/spacemit/ccu_mix.c
224
.set_rate = ccu_mix_set_rate,
drivers/clk/spacemit/ccu_mix.c
235
.set_rate = ccu_factor_set_rate,
drivers/clk/spacemit/ccu_mix.c
257
.set_rate = ccu_mix_set_rate,
drivers/clk/spacemit/ccu_mix.c
271
.set_rate = ccu_mix_set_rate,
drivers/clk/spacemit/ccu_mix.c
281
.set_rate = ccu_mix_set_rate,
drivers/clk/spacemit/ccu_pll.c
262
.set_rate = ccu_pll_set_rate,
drivers/clk/spacemit/ccu_pll.c
273
.set_rate = ccu_plla_set_rate,
drivers/clk/spear/clk-aux-synth.c
133
.set_rate = clk_aux_set_rate,
drivers/clk/spear/clk-frac-synth.c
121
.set_rate = clk_frac_set_rate,
drivers/clk/spear/clk-gpt-synth.c
110
.set_rate = clk_gpt_set_rate,
drivers/clk/spear/clk-vco-pll.c
171
.set_rate = clk_pll_set_rate,
drivers/clk/spear/clk-vco-pll.c
274
.set_rate = clk_vco_set_rate,
drivers/clk/sprd/composite.c
57
.set_rate = sprd_comp_set_rate,
drivers/clk/sprd/div.c
78
.set_rate = sprd_div_set_rate,
drivers/clk/sprd/pll.c
267
.set_rate = sprd_pll_set_rate,
drivers/clk/st/clk-flexgen.c
185
clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate);
drivers/clk/st/clk-flexgen.c
186
ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div);
drivers/clk/st/clk-flexgen.c
188
clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
drivers/clk/st/clk-flexgen.c
189
ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div);
drivers/clk/st/clk-flexgen.c
203
.set_rate = flexgen_set_rate,
drivers/clk/st/clkgen-fsyn.c
439
.set_rate = quadfs_pll_fs660c32_set_rate,
drivers/clk/st/clkgen-fsyn.c
878
.set_rate = quadfs_set_rate,
drivers/clk/st/clkgen-pll.c
638
.set_rate = set_rate_stm_pll3200c32,
drivers/clk/st/clkgen-pll.c
647
.set_rate = set_rate_stm_pll4600c28,
drivers/clk/starfive/clk-starfive-jh7110-pll.c
441
.set_rate = jh7110_pll_set_rate,
drivers/clk/starfive/clk-starfive-jh71x0.c
236
.set_rate = jh71x0_clk_set_rate,
drivers/clk/starfive/clk-starfive-jh71x0.c
243
.set_rate = jh71x0_clk_frac_set_rate,
drivers/clk/starfive/clk-starfive-jh71x0.c
253
.set_rate = jh71x0_clk_set_rate,
drivers/clk/starfive/clk-starfive-jh71x0.c
279
.set_rate = jh71x0_clk_set_rate,
drivers/clk/starfive/clk-starfive-jh71x0.c
291
.set_rate = jh71x0_clk_set_rate,
drivers/clk/stm32/clk-stm32-core.c
396
.set_rate = clk_stm32_divider_set_rate,
drivers/clk/stm32/clk-stm32-core.c
603
.set_rate = clk_stm32_composite_set_rate,
drivers/clk/stm32/clk-stm32mp1.c
1033
.set_rate = timer_ker_set_rate,
drivers/clk/stm32/clk-stm32mp1.c
1089
return clk_divider_ops.set_rate(hw, rate, parent_rate);
drivers/clk/stm32/clk-stm32mp1.c
1106
.set_rate = clk_divider_rtc_set_rate,
drivers/clk/sunxi-ng/ccu_div.c
143
.set_rate = ccu_div_set_rate,
drivers/clk/sunxi-ng/ccu_gate.c
133
.set_rate = ccu_gate_set_rate,
drivers/clk/sunxi-ng/ccu_mp.c
278
.set_rate = ccu_mp_set_rate,
drivers/clk/sunxi-ng/ccu_mp.c
359
.set_rate = ccu_mp_mmc_set_rate,
drivers/clk/sunxi-ng/ccu_mult.c
171
.set_rate = ccu_mult_set_rate,
drivers/clk/sunxi-ng/ccu_nk.c
159
.set_rate = ccu_nk_set_rate,
drivers/clk/sunxi-ng/ccu_nkm.c
269
.set_rate = ccu_nkm_set_rate,
drivers/clk/sunxi-ng/ccu_nkmp.c
232
.set_rate = ccu_nkmp_set_rate,
drivers/clk/sunxi-ng/ccu_nm.c
238
.set_rate = ccu_nm_set_rate,
drivers/clk/sunxi/clk-factors.c
173
.set_rate = clk_factors_set_rate,
drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
221
.set_rate = tcon_ch1_set_rate,
drivers/clk/sunxi/clk-sun9i-cpus.c
177
.set_rate = sun9i_a80_cpus_clk_set_rate,
drivers/clk/tegra/clk-audio-sync.c
42
.set_rate = clk_sync_source_set_rate,
drivers/clk/tegra/clk-bpmp.c
300
.set_rate = tegra_bpmp_clk_set_rate,
drivers/clk/tegra/clk-bpmp.c
311
.set_rate = tegra_bpmp_clk_set_rate,
drivers/clk/tegra/clk-dfll.c
1164
.set_rate = dfll_clk_set_rate,
drivers/clk/tegra/clk-divider.c
137
.set_rate = clk_frac_div_set_rate,
drivers/clk/tegra/clk-periph.c
134
.set_rate = clk_periph_set_rate,
drivers/clk/tegra/clk-periph.c
158
.set_rate = clk_periph_set_rate,
drivers/clk/tegra/clk-periph.c
69
return div_ops->set_rate(div_hw, rate, parent_rate);
drivers/clk/tegra/clk-pll.c
1066
.set_rate = clk_pll_set_rate,
drivers/clk/tegra/clk-pll.c
1204
.set_rate = clk_pll_set_rate,
drivers/clk/tegra/clk-pll.c
2017
.set_rate = clk_pllxc_set_rate,
drivers/clk/tegra/clk-pll.c
2026
.set_rate = clk_pllc_set_rate,
drivers/clk/tegra/clk-pll.c
2035
.set_rate = clk_pllre_set_rate,
drivers/clk/tegra/clk-pll.c
2335
.set_rate = clk_pllxc_set_rate,
drivers/clk/tegra/clk-sdmmc-mux.c
226
.set_rate = clk_sdmmc_mux_set_rate,
drivers/clk/tegra/clk-super.c
175
return super->div_ops->set_rate(div_hw, rate, parent_rate);
drivers/clk/tegra/clk-super.c
195
.set_rate = clk_super_set_rate,
drivers/clk/tegra/clk-tegra-super-cclk.c
121
.set_rate = cclk_super_set_rate,
drivers/clk/tegra/clk-tegra-super-cclk.c
46
return tegra_clk_super_ops.set_rate(hw, rate, parent_rate);
drivers/clk/tegra/clk-tegra124-emc.c
481
.set_rate = emc_set_rate,
drivers/clk/tegra/clk-tegra20-emc.c
219
.set_rate = emc_set_rate,
drivers/clk/tegra/clk-tegra210-emc.c
234
err = provider->set_rate(dev, config);
drivers/clk/tegra/clk-tegra210-emc.c
271
.set_rate = tegra210_clk_emc_set_rate,
drivers/clk/thead/clk-th1520-ap.c
319
.set_rate = ccu_div_set_rate,
drivers/clk/thead/clk-th1520-ap.c
477
.set_rate = ccu_pll_set_rate,
drivers/clk/thead/clk-th1520-ap.c
542
.set_rate = c910_clk_set_rate,
drivers/clk/ti/clk-dra7-atl.c
162
.set_rate = atl_clk_set_rate,
drivers/clk/ti/composite.c
44
.set_rate = &ti_composite_set_rate,
drivers/clk/ti/divider.c
305
.set_rate = ti_clk_divider_set_rate,
drivers/clk/ti/dpll.c
110
.set_rate = &omap3_dpll5_set_rate,
drivers/clk/ti/dpll.c
121
.set_rate = &omap3_dpll4_set_rate,
drivers/clk/ti/dpll.c
28
.set_rate = &omap3_noncore_dpll_set_rate,
drivers/clk/ti/dpll.c
50
.set_rate = &omap3_noncore_dpll_set_rate,
drivers/clk/ti/dpll.c
62
.set_rate = &omap3_noncore_dpll_set_rate,
drivers/clk/ti/dpll.c
81
.set_rate = &omap2_reprogram_dpllcore,
drivers/clk/ti/dpll.c
99
.set_rate = &omap3_noncore_dpll_set_rate,
drivers/clk/ti/fapll.c
275
.set_rate = ti_fapll_set_rate,
drivers/clk/ti/fapll.c
487
.set_rate = ti_fapll_synth_set_rate,
drivers/clk/ux500/clk-prcmu.c
163
.set_rate = clk_prcmu_set_rate,
drivers/clk/ux500/clk-prcmu.c
175
.set_rate = clk_prcmu_set_rate,
drivers/clk/ux500/clk-prcmu.c
193
.set_rate = clk_prcmu_set_rate,
drivers/clk/versatile/clk-icst.c
351
.set_rate = icst_set_rate,
drivers/clk/versatile/clk-vexpress-osc.c
61
.set_rate = vexpress_osc_set_rate,
drivers/clk/visconti/pll.c
242
.set_rate = visconti_pll_set_rate,
drivers/clk/x86/clk-cgu.c
185
.set_rate = lgm_clk_divider_set_rate,
drivers/clk/x86/clk-cgu.c
533
.set_rate = lgm_clk_ddiv_set_rate,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
702
.set_rate = clk_wzrd_ver_dynamic_reconfig,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
708
.set_rate = clk_wzrd_dynamic_all_ver,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
714
.set_rate = clk_wzrd_dynamic_reconfig,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
720
.set_rate = clk_wzrd_dynamic_all,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
789
.set_rate = clk_wzrd_dynamic_reconfig_f,
drivers/clk/xilinx/xlnx_vcu.c
402
.set_rate = xvcu_pll_set_rate,
drivers/clk/zynqmp/divider.c
206
.set_rate = zynqmp_clk_divider_set_rate,
drivers/clk/zynqmp/pll.c
298
.set_rate = zynqmp_pll_set_rate,
drivers/clocksource/ingenic-sysost.c
184
.set_rate = ingenic_ost_percpu_timer_set_rate,
drivers/clocksource/ingenic-sysost.c
190
.set_rate = ingenic_ost_global_timer_set_rate,
drivers/firmware/samsung/exynos-acpm.c
599
dvfs_ops->set_rate = acpm_dvfs_set_rate;
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
528
phy_cfg.dp.set_rate = true;
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
1005
phy_cfg.dp.set_rate = false;
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
1126
phy_cfg.dp.set_rate = false;
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
837
phy_cfg.dp.set_rate = true;
drivers/gpu/drm/bridge/synopsys/dw-dp.c
573
phy_cfg.dp.set_rate = false;
drivers/gpu/drm/bridge/synopsys/dw-dp.c
610
phy_cfg.dp.set_rate = true;
drivers/gpu/drm/imx/ipuv3/imx-tve.c
416
.set_rate = clk_tve_di_set_rate,
drivers/gpu/drm/mcde/mcde_clk_div.c
139
.set_rate = mcde_clk_div_set_rate,
drivers/gpu/drm/mediatek/mtk_dp.c
1263
.set_rate = 1,
drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c
125
.set_rate = mdp4_lvds_pll_set_rate,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
460
.set_rate = dsi_pll_10nm_vco_set_rate,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
594
.set_rate = dsi_pll_14nm_vco_set_rate,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
679
.set_rate = dsi_pll_14nm_postdiv_set_rate,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
550
.set_rate = dsi_pll_28nm_clk_set_rate,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
559
.set_rate = dsi_pll_28nm_clk_set_rate,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
568
.set_rate = dsi_pll_28nm_clk_set_rate,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
247
.set_rate = dsi_pll_28nm_clk_set_rate,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
332
.set_rate = clk_bytediv_set_rate,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
621
.set_rate = dsi_pll_7nm_vco_set_rate,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
682
.set_rate = hdmi_8996_pll_set_clk_rate,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
686
.set_rate = hdmi_8998_pll_set_clk_rate,
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
408
.set_rate = hdmi_pll_set_rate,
drivers/gpu/drm/pl111/pl111_display.c
536
.set_rate = pl111_clk_div_set_rate,
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
357
.set_rate = dw_mipi_dsi_clk_set_rate,
drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
107
.set_rate = sun4i_ddc_set_rate,
drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
197
.set_rate = sun4i_tmds_set_rate,
drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c
161
.set_rate = sun4i_dclk_set_rate,
drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c
137
.set_rate = sun8i_phy_clk_set_rate,
drivers/hwmon/ltc4282.c
1100
.set_rate = ltc4282_set_rate,
drivers/i2c/busses/i2c-bcm2835.c
160
.set_rate = clk_bcm2835_i2c_set_rate,
drivers/iio/frequency/adf4350.c
456
.set_rate = adf4350_clk_set_rate,
drivers/iio/frequency/adf4377.c
997
.set_rate = adf4377_clk_set_rate,
drivers/input/mouse/cypress_ps2.c
656
psmouse->set_rate = cypress_set_rate;
drivers/input/mouse/elantech.c
2094
etd->original_set_rate = psmouse->set_rate;
drivers/input/mouse/elantech.c
2095
psmouse->set_rate = elantech_set_rate_restore_reg_07;
drivers/input/mouse/focaltech.c
445
psmouse->set_rate = focaltech_set_rate;
drivers/input/mouse/psmouse-base.c
1288
psmouse->set_rate(psmouse, psmouse->rate);
drivers/input/mouse/psmouse-base.c
1990
psmouse->set_rate(psmouse, value);
drivers/input/mouse/psmouse-base.c
980
psmouse->set_rate = psmouse_set_rate;
drivers/input/mouse/psmouse.h
119
void (*set_rate)(struct psmouse *psmouse, unsigned int rate);
drivers/input/mouse/synaptics.c
1658
psmouse->set_rate = synaptics_set_rate;
drivers/media/i2c/ds90ub953.c
1056
.set_rate = ub953_clkout_set_rate,
drivers/media/i2c/max96717.c
850
.set_rate = max96717_clk_set_rate,
drivers/media/i2c/tc358746.c
1252
.set_rate = tc358746_mclk_set_rate,
drivers/media/platform/microchip/microchip-isc-clk.c
226
.set_rate = isc_clk_set_rate,
drivers/media/platform/ti/omap3isp/isp.c
279
.set_rate = isp_xclk_set_rate,
drivers/memory/tegra/tegra210-emc-core.c
1921
emc->provider.set_rate = tegra210_emc_set_rate;
drivers/net/ethernet/cadence/macb_main.c
5183
.set_rate = fu540_macb_tx_set_rate,
drivers/net/ethernet/qlogic/qed/qed_sriov.c
5303
.set_rate = &qed_set_vf_rate,
drivers/net/ethernet/qlogic/qede/qede_main.c
473
return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
drivers/net/ethernet/renesas/ravb.h
1039
void (*set_rate)(struct net_device *ndev);
drivers/net/ethernet/renesas/ravb_main.c
1454
info->set_rate(ndev);
drivers/net/ethernet/renesas/ravb_main.c
2673
.set_rate = ravb_set_rate_rcar,
drivers/net/ethernet/renesas/ravb_main.c
2697
.set_rate = ravb_set_rate_rcar,
drivers/net/ethernet/renesas/ravb_main.c
2724
.set_rate = ravb_set_rate_rcar,
drivers/net/ethernet/renesas/ravb_main.c
2751
.set_rate = ravb_set_rate_rcar,
drivers/net/ethernet/renesas/ravb_main.c
2777
.set_rate = ravb_set_rate_gbeth,
drivers/net/ethernet/renesas/sh_eth.c
1023
.set_rate = sh_eth_set_rate_gether,
drivers/net/ethernet/renesas/sh_eth.c
1508
if (mdp->cd->set_rate)
drivers/net/ethernet/renesas/sh_eth.c
1509
mdp->cd->set_rate(ndev);
drivers/net/ethernet/renesas/sh_eth.c
1961
if (mdp->cd->set_rate)
drivers/net/ethernet/renesas/sh_eth.c
1962
mdp->cd->set_rate(ndev);
drivers/net/ethernet/renesas/sh_eth.c
591
.set_rate = sh_eth_set_rate_gether,
drivers/net/ethernet/renesas/sh_eth.c
651
.set_rate = sh_eth_set_rate_rcar,
drivers/net/ethernet/renesas/sh_eth.c
682
.set_rate = sh_eth_set_rate_rcar,
drivers/net/ethernet/renesas/sh_eth.c
718
.set_rate = sh_eth_set_rate_gether,
drivers/net/ethernet/renesas/sh_eth.c
762
.set_rate = sh_eth_set_rate_rcar,
drivers/net/ethernet/renesas/sh_eth.c
814
.set_rate = sh_eth_set_rate_sh7724,
drivers/net/ethernet/renesas/sh_eth.c
858
.set_rate = sh_eth_set_rate_sh7757,
drivers/net/ethernet/renesas/sh_eth.c
936
.set_rate = sh_eth_set_rate_giga,
drivers/net/ethernet/renesas/sh_eth.c
980
.set_rate = sh_eth_set_rate_gether,
drivers/net/ethernet/renesas/sh_eth.h
482
void (*set_rate)(struct net_device *ndev);
drivers/peci/controller/peci-aspeed.c
398
.set_rate = clk_aspeed_peci_set_rate,
drivers/phy/apple/atc.c
1909
if (opts->set_rate) {
drivers/phy/cadence/phy-cadence-torrent.c
1375
if (dp->set_rate) {
drivers/phy/cadence/phy-cadence-torrent.c
1629
if (opts->dp.set_rate) {
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
606
.set_rate = fsl_samsung_hdmi_phy_clk_set_rate,
drivers/phy/mediatek/phy-mtk-dp.c
114
if (opts->dp.set_rate) {
drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
172
.set_rate = mtk_hdmi_pll_set_rate,
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
225
.set_rate = mtk_hdmi_pll_set_rate,
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
441
.set_rate = mtk_hdmi_pll_set_rate,
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
252
.set_rate = mtk_mipi_tx_pll_set_rate,
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
112
.set_rate = mtk_mipi_tx_pll_set_rate,
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
636
inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
840
.set_rate = inno_hdmi_phy_rk3228_clk_set_rate,
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
995
.set_rate = inno_hdmi_phy_rk3328_clk_set_rate,
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
1797
if (dp->set_rate) {
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
2097
if (opts->dp.set_rate) {
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
2371
.set_rate = rk_hdptx_phy_clk_set_rate,
drivers/phy/rockchip/phy-rockchip-usbdp.c
1204
if (dp->set_rate) {
drivers/phy/rockchip/phy-rockchip-usbdp.c
1222
if (dp->set_rate) {
drivers/phy/ti/phy-j721e-wiz.c
963
.set_rate = wiz_clk_div_set_rate,
drivers/rtc/rtc-ac100.c
304
.set_rate = ac100_clkout_set_rate,
drivers/rtc/rtc-ds1307.c
1545
.set_rate = ds3231_clk_sqw_set_rate,
drivers/rtc/rtc-hym8563.c
372
.set_rate = hym8563_clkout_set_rate,
drivers/rtc/rtc-m41t80.c
569
.set_rate = m41t80_sqw_set_rate,
drivers/rtc/rtc-max31335.c
558
.set_rate = max31335_clkout_set_rate,
drivers/rtc/rtc-nct3018y.c
455
.set_rate = nct3018y_clkout_set_rate,
drivers/rtc/rtc-pcf85063.c
495
.set_rate = pcf85063_clkout_set_rate,
drivers/rtc/rtc-pcf8563.c
422
.set_rate = pcf8563_clkout_set_rate,
drivers/rtc/rtc-rv3028.c
811
.set_rate = rv3028_clkout_set_rate,
drivers/rtc/rtc-rv3032.c
747
.set_rate = rv3032_clkout_set_rate,
drivers/sh/clk/core.c
490
if (likely(clk->ops && clk->ops->set_rate)) {
drivers/sh/clk/core.c
491
ret = clk->ops->set_rate(clk, rate);
drivers/sh/clk/core.c
583
if (likely(clkp->ops->set_rate))
drivers/sh/clk/core.c
584
clkp->ops->set_rate(clkp, rate);
drivers/sh/clk/cpg.c
185
.set_rate = sh_clk_div_set_rate,
drivers/sh/clk/cpg.c
191
.set_rate = sh_clk_div_set_rate,
drivers/sh/clk/cpg.c
318
.set_rate = sh_clk_div_set_rate,
drivers/sh/clk/cpg.c
370
.set_rate = sh_clk_div_set_rate,
drivers/sh/clk/cpg.c
450
.set_rate = fsidiv_set_rate,
drivers/spi/spi-meson-spicc.c
820
return clk_divider_ops.set_rate(hw, rate, parent_rate);
drivers/spi/spi-meson-spicc.c
826
.set_rate = meson_spicc_pow2_set_rate,
drivers/staging/media/deprecated/atmel/atmel-isc-clk.c
226
.set_rate = isc_clk_set_rate,
drivers/tty/serial/mvebu-uart.c
1299
.set_rate = mvebu_uart_clock_set_rate,
drivers/tty/serial/qcom_geni_serial.c
113
int (*set_rate)(struct uart_port *uport, unsigned int baud);
drivers/tty/serial/qcom_geni_serial.c
1364
ret = port->dev_data->set_rate(uport, baud);
drivers/tty/serial/qcom_geni_serial.c
1988
.set_rate = geni_serial_set_rate,
drivers/tty/serial/qcom_geni_serial.c
1996
.set_rate = geni_serial_set_rate,
drivers/tty/serial/qcom_geni_serial.c
2009
.set_rate = geni_serial_set_level,
drivers/tty/serial/qcom_geni_serial.c
2021
.set_rate = geni_serial_set_level,
drivers/tty/synclink_gt.c
3819
set_rate(info, info->params.clock_speed);
drivers/tty/synclink_gt.c
3821
set_rate(info, 3686400);
drivers/tty/synclink_gt.c
4128
set_rate(info, info->params.data_rate * 8);
drivers/tty/synclink_gt.c
4131
set_rate(info, info->params.data_rate * 16);
drivers/tty/synclink_gt.c
4329
set_rate(info, info->params.clock_speed * 16);
drivers/tty/synclink_gt.c
4332
set_rate(info, info->params.clock_speed);
drivers/tty/synclink_gt.c
439
static void set_rate(struct slgt_info *info, u32 data_rate);
include/linux/clk-provider.h
253
int (*set_rate)(struct clk_hw *hw, unsigned long rate,
include/linux/clk/tegra.h
176
int (*set_rate)(struct device *dev,
include/linux/firmware/samsung/exynos-acpm-protocol.h
17
int (*set_rate)(const struct acpm_handle *handle,
include/linux/phy/phy-dp.h
76
u8 set_rate : 1;
include/linux/qed/qed_iov_if.h
28
int (*set_rate) (struct qed_dev *cdev, int vfid,
include/linux/sh_clk.h
29
int (*set_rate)(struct clk *clk, unsigned long rate);
sound/firewire/oxfw/oxfw-stream.c
88
return set_rate(oxfw, rate);
sound/pci/ice1712/ice1712.h
373
void (*set_rate)(struct snd_ice1712 *ice, unsigned int rate);
sound/pci/ice1712/ice1724.c
2569
if (!ice->set_rate)
sound/pci/ice1712/ice1724.c
2570
ice->set_rate = stdclock_set_rate;
sound/pci/ice1712/ice1724.c
657
ice->set_rate(ice, rate);
sound/pci/ice1712/juli.c
611
ice->set_rate = juli_set_rate;
sound/pci/ice1712/maya44.c
692
ice->gpio.set_pro_rate = set_rate;
sound/pci/ice1712/quartet.c
979
ice->set_rate = qtet_set_rate;
sound/soc/codecs/da7219.c
2125
.set_rate = da7219_wclk_set_rate,
sound/soc/codecs/da7219.c
2130
.set_rate = da7219_bclk_set_rate,
sound/soc/codecs/rt5682.c
2855
.set_rate = rt5682_wclk_set_rate,
sound/soc/codecs/rt5682.c
2860
.set_rate = rt5682_bclk_set_rate,
sound/soc/codecs/rt5682s.c
2777
.set_rate = rt5682s_wclk_set_rate,
sound/soc/codecs/rt5682s.c
2782
.set_rate = rt5682s_bclk_set_rate,
sound/soc/codecs/tlv320aic32x4-clk.c
271
.set_rate = clk_aic32x4_pll_set_rate,
sound/soc/codecs/tlv320aic32x4-clk.c
365
.set_rate = clk_aic32x4_div_set_rate,
sound/soc/codecs/tlv320aic32x4-clk.c
393
.set_rate = clk_aic32x4_div_set_rate,
sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c
81
.set_rate = clk_q6dsp_set_rate,
sound/soc/renesas/fsi.c
239
int (*set_rate)(struct device *dev,
sound/soc/renesas/fsi.c
717
int (*set_rate)(struct device *dev,
sound/soc/renesas/fsi.c
728
clock->set_rate = set_rate;
sound/soc/renesas/fsi.c
784
return fsi->clock.set_rate &&
sound/soc/renesas/fsi.c
798
ret = clock->set_rate(dev, fsi);
sound/soc/stm/stm32_i2s.c
536
.set_rate = stm32_i2smclk_set_rate,
sound/soc/stm/stm32_sai_sub.c
564
.set_rate = stm32_sai_mclk_set_rate,
sound/spi/at73c213.c
179
goto set_rate;
sound/spi/at73c213.c
187
set_rate:
sound/usb/6fire/control.c
562
rt->set_rate = usb6fire_control_set_rate;
sound/usb/6fire/control.h
31
int (*set_rate)(struct control_runtime *rt, int rate);
sound/usb/6fire/pcm.c
84
ret = ctrl_rt->set_rate(ctrl_rt, rt->rate);