set_hca_cap
ret = mlx5_cmd_exec_in(dev, set_hca_cap, hca_cap);
ret = mlx5_cmd_exec_in(dev, set_hca_cap, hca_cap);
ret = mlx5_cmd_exec_in(esw->dev, set_hca_cap, hca_cap);
err = set_hca_cap(dev);
return mlx5_cmd_exec_in(dev, set_hca_cap, in);
void *set_hca_cap;
set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
void *set_hca_cap;
set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
MLX5_SET(odp_cap, set_hca_cap, mem_page_fault, mem_page_fault);
MLX5_SET(odp_cap, set_hca_cap, field, _res); \
void *set_hca_cap;
set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
MLX5_SET(cmd_hca_cap_2, set_hca_cap, lag_per_mp_group, 1);
void *set_hca_cap;
set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
set_hca_cap,
MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
MLX5_SET(cmd_hca_cap, set_hca_cap,
MLX5_SET(cmd_hca_cap, set_hca_cap,
set_hca_cap,
MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
mlx5_vhca_state_cap_handle(dev, set_hca_cap);
MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
MLX5_SET(cmd_hca_cap, set_hca_cap, abs_native_port_num, 1);
void *set_hca_cap;
set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1);
void *set_hca_cap;
set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
ret = mlx5_cmd_exec_in(dev, set_hca_cap, hca_cap);
void mlx5_vhca_state_cap_handle(struct mlx5_core_dev *dev, void *set_hca_cap)
MLX5_SET(cmd_hca_cap, set_hca_cap, vhca_state, 1);
MLX5_SET(cmd_hca_cap, set_hca_cap, event_on_vhca_state_allocated, 1);
MLX5_SET(cmd_hca_cap, set_hca_cap, event_on_vhca_state_active, 1);
MLX5_SET(cmd_hca_cap, set_hca_cap, event_on_vhca_state_in_use, 1);
MLX5_SET(cmd_hca_cap, set_hca_cap, event_on_vhca_state_teardown_request, 1);
void mlx5_vhca_state_cap_handle(struct mlx5_core_dev *dev, void *set_hca_cap);
static inline void mlx5_vhca_state_cap_handle(struct mlx5_core_dev *dev, void *set_hca_cap)
void *set_hca_cap;
set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
memcpy(set_hca_cap, hca_cap, MLX5_ST_SZ_BYTES(cmd_hca_cap));
ret = mlx5_cmd_exec_in(dev, set_hca_cap, set_ctx);