s5h1411_writereg
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4);
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val);
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val);
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0);
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0);
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0,
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0);
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0);
s5h1411_writereg(state, init_tab[i].addr,
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);