drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1463

u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1479

sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1480

sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1498

sdma_v7_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1545

u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1666

RREG32(sdma_v7_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

234

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

238

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

404

rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

406

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

407

ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

409

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

459

mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

461

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

490

rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

498

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

502

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

503

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

504

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

505

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

507

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

508

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

509

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

510

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

514

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

516

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

520

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

522

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

533

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

534

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

540

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

543

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

544

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

547

doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

548

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

557

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

558

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

569

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

572

temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

576

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

579

temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

582

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

585

temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

590

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

594

temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

597

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

602

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

604

ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

610

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

718

tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

720

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

722

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

724

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

727

tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

729

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

734

sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

736

sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

764

tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

767

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

769

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

899

m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 0,