drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1508

u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1524

sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1525

sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1543

sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1611

u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1734

RREG32(sdma_v6_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

233

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

236

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

401

rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

403

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

404

ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

406

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

437

f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

440

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

467

f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

469

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

495

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

499

rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

507

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

511

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

512

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

513

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

514

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

516

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

517

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

518

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

519

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

523

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

525

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

529

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

531

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

538

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

539

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

545

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

548

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

549

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

552

doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

553

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

562

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

563

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

574

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

577

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

581

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

584

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

587

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

590

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

596

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

600

temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

603

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

608

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

610

ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

616

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

694

WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

699

WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

709

WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

714

WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

728

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

733

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

736

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

745

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

750

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

753

WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

769

tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

771

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

772

tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

775

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

777

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

880

m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,