drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1415

u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1431

sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1432

sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1433

sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1434

sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1482

freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1484

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1487

freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1496

stat1_reg = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1504

f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1506

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1508

cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1510

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1526

freeze = RREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1528

WREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1546

sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1588

u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1724

def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1732

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1735

def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1743

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1762

def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1765

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1769

def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1772

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1822

data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1827

data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1898

RREG32(sdma_v5_2_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

195

wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

197

wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

235

WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

237

WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

248

WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

250

WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

419

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

421

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

422

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

424

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

479

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

481

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

483

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

488

f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

491

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

519

f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

521

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

551

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

555

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

562

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

566

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

567

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

568

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

569

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

571

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

572

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

573

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

574

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

579

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

581

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

583

wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

588

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

592

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

594

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

599

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

600

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

606

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

609

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

610

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

613

doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

614

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

623

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

624

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

635

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

640

temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

645

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

648

temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

651

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

654

temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

660

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

663

temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

665

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

670

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

672

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

678

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

752

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

757

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

760

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

875

m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

886

m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,