drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1502

u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1518

sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1519

sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1574

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1576

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1579

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1587

stat1_reg = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1595

f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1597

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1599

cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1601

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1616

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1618

WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1682

sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1683

sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1758

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1768

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1771

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1781

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1795

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1798

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1802

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1805

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1850

data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1855

data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1896

RREG32(sdma_v5_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

355

wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

357

wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

398

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

401

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

569

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

571

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

572

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

574

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

629

f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

635

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

637

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

639

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

643

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

672

f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

674

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

702

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

706

rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

713

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

717

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

718

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

719

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

720

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

722

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

723

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

724

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

725

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

729

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

731

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

733

wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

738

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

742

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

744

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

749

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

751

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

758

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

761

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

763

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

767

doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

768

doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

778

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

779

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

789

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

793

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

798

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

801

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

804

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

807

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

811

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

816

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

818

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

823

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

825

ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

831

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

905

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

910

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

913

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

975

m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

986

m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,