rxcfg
sw32(rxcfg, rx_flags);
sw32(rxcfg, sr32(rxcfg) | RxATX);
u32 rxcfg = 0;
rxcfg |= MAC_RX_CFG_PROMISC_EN;
rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
return rxcfg;
u32 rxcfg, rxcfg_new;
rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
rxcfg |= rxcfg_new;
writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
u32 rxcfg = 0;
rxcfg |= MAC_RXCFG_HFE;
rxcfg |= MAC_RXCFG_PROM;
rxcfg |= MAC_RXCFG_HFE;
return rxcfg;
u32 rxcfg, rxcfg_new;
rxcfg = readl(gp->regs + MAC_RXCFG);
writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
rxcfg |= rxcfg_new;
writel(rxcfg, gp->regs + MAC_RXCFG);
u32 regtmp, rxcfg;
rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
rxcfg |= BIGMAC_RXCFG_PMISC;
hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
u32 rxcfg_reg, rxcfg;
rxcfg = PRUSS_MII_RT_RXCFG_RX_ENABLE |
regmap_write(mii_rt, rxcfg_reg, rxcfg);
rxcfg |= PRUSS_MII_RT_RXCFG_RX_MUX_SEL;
regmap_write(mii_rt, rxcfg_reg, rxcfg);
u32 rxcfg = TSI_READ(TSI108_EC_RXCFG);
rxcfg &= ~(TSI108_EC_RXCFG_UC_HASH | TSI108_EC_RXCFG_MC_HASH);
rxcfg |= TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE;
rxcfg &= ~(TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE);
rxcfg |= TSI108_EC_RXCFG_MFE | TSI108_EC_RXCFG_MC_HASH;
TSI_WRITE(TSI108_EC_RXCFG, rxcfg);
int txcfg = 0, rxcfg = 0;
rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
PTP_RX_PARSE_CONFIG, rxcfg);
int txcfg = 0, rxcfg = 0;
rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
int txcfg = 0, rxcfg = 0;
rxcfg = MCHP_RDS_PTP_PARSE_CONFIG_LAYER2_EN;
rxcfg |= MCHP_RDS_PTP_PARSE_CONFIG_IPV4_EN |
MCHP_RDS_PTP_PORT, rxcfg);