rx_state
bcsp->rx_state != BCSP_W4_CRC)
bcsp->rx_state != BCSP_W4_CRC)
bcsp->rx_state != BCSP_W4_CRC)
bcsp->rx_state = BCSP_W4_PKT_DELIMITER;
bcsp->rx_state = BCSP_W4_PKT_DELIMITER;
hu, count, bcsp->rx_state, bcsp->rx_count);
bcsp->rx_state = BCSP_W4_PKT_START;
} rx_state;
switch (bcsp->rx_state) {
bcsp->rx_state = BCSP_W4_PKT_DELIMITER;
bcsp->rx_state = BCSP_W4_DATA;
bcsp->rx_state = BCSP_W4_CRC;
bcsp->rx_state = BCSP_W4_PKT_DELIMITER;
bcsp->rx_state = BCSP_W4_PKT_START;
bcsp->rx_state = BCSP_W4_BCSP_HDR;
bcsp->rx_state = BCSP_W4_PKT_DELIMITER;
bcsp->rx_state = BCSP_W4_PKT_DELIMITER;
enum tegra_ivc_state rx_state, tx_state;
rx_state = tegra_ivc_header_read_field(&ivc->rx.map, tx.state);
if (rx_state == TEGRA_IVC_STATE_SYNC) {
rx_state == TEGRA_IVC_STATE_ACK) {
enum can_state new_state, rx_state, tx_state;
can_state_get_by_berr_counter(dev, &bec, &tx_state, &rx_state);
rx_state = CAN_STATE_BUS_OFF;
new_state = max(tx_state, rx_state);
can_change_state(dev, cf, tx_state, rx_state);
enum can_state rx_state, tx_state;
rx_state = bec.txerr <= bec.rxerr ? new_state : 0;
can_change_state(ndev, cf, tx_state, rx_state);
enum can_state *rx_state)
*rx_state = can_state_err_to_state(bec->rxerr);
enum can_state tx_state, enum can_state rx_state)
enum can_state new_state = max(tx_state, rx_state);
cf->data[1] |= tx_state >= rx_state ?
cf->data[1] |= tx_state <= rx_state ?
can_rx_state_to_frame(dev, rx_state) : 0;
enum can_state tx_state, rx_state;
rx_state = (rxerr >= txerr) ?
can_change_state(core->netdev, cf, tx_state, rx_state);
enum can_state new_state, rx_state, tx_state;
rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
new_state = max(tx_state, rx_state);
rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
can_change_state(dev, cf, tx_state, rx_state);
enum can_state rx_state)
can_change_state(can->can.dev, cf, tx_state, rx_state);
enum can_state *rx_state)
*rx_state = bec->txerr <= bec->rxerr ? *new_state : 0;
enum can_state old_state, new_state, tx_state, rx_state;
kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
kvaser_pciefd_change_state(can, &bec, cf, new_state, tx_state, rx_state);
enum can_state old_state, new_state, tx_state, rx_state;
kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
kvaser_pciefd_change_state(can, &bec, cf, new_state, tx_state, rx_state);
enum can_state rx_state, tx_state, state = priv->can.state;
rx_state = txerr <= rxerr ? state : 0;
can_change_state(ndev, cf, tx_state, rx_state);
enum can_state new_state, rx_state, tx_state;
can_state_get_by_berr_counter(ndev, &bec, &tx_state, &rx_state);
new_state = max(tx_state, rx_state);
can_change_state(ndev, cf, tx_state, rx_state);
enum can_state state, rx_state, tx_state;
can_state_get_by_berr_counter(dev, &bec, &tx_state, &rx_state);
rx_state = CAN_STATE_BUS_OFF;
state = max(tx_state, rx_state);
can_change_state(dev, cf, tx_state, rx_state);
enum can_state state, rx_state, tx_state;
rx_state = txerr <= rxerr ? state : 0;
can_change_state(dev, cf, tx_state, rx_state);
enum can_state rx_state, tx_state;
rx_state = txerr <= rxerr ? new_state : 0;
can_change_state(net, cf, tx_state, rx_state);
enum can_state new_state, rx_state, tx_state;
rx_state = CAN_STATE_ERROR_PASSIVE;
rx_state = CAN_STATE_ERROR_WARNING;
rx_state = CAN_STATE_ERROR_ACTIVE;
new_state = max(tx_state, rx_state);
can_change_state(priv->ndev, cf, tx_state, rx_state);
enum can_state rx_state, tx_state;
rx_state = txerr <= rxerr ? state : 0;
can_change_state(dev, cf, tx_state, rx_state);
enum can_state rx_state,
priv->can.state = max(tx_state, rx_state);
can_change_state(priv->ndev, cf, tx_state, rx_state);
if (max(tx_state, rx_state) != CAN_STATE_BUS_OFF) {
enum can_state rx_state, tx_state;
rx_state = rec >= tec ? CAN_STATE_ERROR_WARNING : 0;
ti_hecc_change_state(ndev, rx_state, tx_state);
rx_state = rec >= tec ? CAN_STATE_ERROR_PASSIVE : 0;
ti_hecc_change_state(ndev, rx_state, tx_state);
rx_state = CAN_STATE_BUS_OFF;
ti_hecc_change_state(ndev, rx_state, tx_state);
enum can_state new_state, tx_state, rx_state;
rx_state = rec >= tec ? new_state : 0;
ti_hecc_change_state(ndev, rx_state, tx_state);
enum can_state tx_state, rx_state;
rx_state = (priv->bec.txerr <= priv->bec.rxerr) ? new_state : 0;
tx_state, rx_state);
enum can_state tx_state, rx_state;
rx_state = data->txerr <= data->rxerr ? can_state : 0;
can_change_state(netdev, cf, tx_state, rx_state);
enum can_state tx_state, rx_state;
rx_state = (bec->txerr <= bec->rxerr) ?
can_change_state(netdev, cf, tx_state, rx_state);
enum can_state cur_state, new_state, tx_state, rx_state;
rx_state = (es->txerr <= es->rxerr) ? new_state : 0;
can_change_state(priv->netdev, cf, tx_state, rx_state);
enum can_state new_state, rx_state, tx_state;
can_state_get_by_berr_counter(ndev, &bec, &tx_state, &rx_state);
new_state = max(tx_state, rx_state);
can_change_state(ndev, cf, tx_state, rx_state);
enum can_state rx_state =
can_change_state(mc->netdev, cf, tx_state, rx_state);
enum can_state rx_state, tx_state;
rx_state = (pdev->bec.txerr <= pdev->bec.rxerr) ? new_state : 0;
can_change_state(netdev, cf, tx_state, rx_state);
enum can_state rx_state = txerr <= rxerr ? new_state : 0;
can_change_state(ndev, cf, tx_state, rx_state);
(serial->rx_state == RX_PENDING))) {
serial->rx_state = RX_SENT;
serial->rx_state = RX_IDLE;
serial->rx_state = RX_IDLE;
if (serial->rx_state == RX_IDLE &&
serial->rx_state = RX_SENT;
serial->rx_state = RX_PENDING;
enum rx_ctrl_state rx_state;
u8 rx_state);
u8 rx_state = 0;
rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
else if (rx_state ==
rx_state);
if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
else if (rx_state ==
rx_state);
bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state);
u8 rx_state)
if (rx_state == FCOE_TASK_RX_STATE_IGNORED_SEQUENCE_CLEANUP) {
__be32 rx_state; /* 0x94, RX state, initialize to 0 */
iowrite32be(0, &uccup->rx_state);
out_be32(&fhci->pram->rx_state, 0);
__be32 rx_state; /* Rx internal state */
enum can_state *rx_state);
enum can_state tx_state, enum can_state rx_state);
enum rx_state state;
unsigned long rx_state;
unsigned long rx_state;
__u8 rx_state;
chan->rx_state == L2CAP_RX_STATE_RECV) {
chan->rx_state = L2CAP_RX_STATE_RECV;
if (chan->rx_state == L2CAP_RX_STATE_SREJ_SENT) {
if (chan->rx_state == L2CAP_RX_STATE_SREJ_SENT) {
chan->rx_state = L2CAP_RX_STATE_RECV;
chan->rx_state = L2CAP_RX_STATE_RECV;
if (chan->rx_state == L2CAP_RX_STATE_SREJ_SENT) {
chan->rx_state = L2CAP_RX_STATE_SREJ_SENT;
chan->rx_state = L2CAP_RX_STATE_RECV;
chan->rx_state = L2CAP_RX_STATE_RECV;
control, skb, event, chan->rx_state);
switch (chan->rx_state) {
chan->rx_state);