arch/arc/plat-hsdk/platform.c

213

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));

arch/arc/plat-hsdk/platform.c

219

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));

arch/arc/plat-hsdk/platform.c

237

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));

arch/arc/plat-hsdk/platform.c

243

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));

arch/arc/plat-hsdk/platform.c

249

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));

arch/arc/plat-hsdk/platform.c

255

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));

arch/arc/plat-hsdk/platform.c

261

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));

arch/arc/plat-hsdk/platform.c

267

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));

arch/arc/plat-hsdk/platform.c

273

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));

arch/arc/plat-hsdk/platform.c

279

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));

arch/arc/plat-hsdk/platform.c

285

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));

arch/arc/plat-hsdk/platform.c

291

writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));