rtw_write32_clr
rtw_write32_clr(rtwdev, REG_EFUSE_CTRL, BIT_EF_FLAG);
rtw_write32_clr(rtwdev, REG_RCR, BIT_DISGCLK);
rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9));
rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN);
rtw_write32_clr(rtwdev, REG_FWHW_TXQ_CTRL,
rtw_write32_clr(rtwdev, REG_TCR, BIT_TCR_UPDATE_HGQMD);
rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
rtw_write32_clr(rtwdev, REG_TCR, BIT_PWRMGT_HWDATA_EN);
rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF);
rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF);
rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL);
rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0);
rtw_write32_clr(rtwdev, REG_CCASEL, BIT(31));
rtw_write32_clr(rtwdev, REG_CCASEL, BIT(31));
rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, BIT(15));
rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
rtw_write32_clr(rtwdev, REG_CCK_RPT_FORMAT, BIT(2));
rtw_write32_clr(rtwdev, REG_BCN_CTRL,
rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT,
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN);
rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN);
rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN);
rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS);
rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT);
rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT);
rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
rtw_write32_clr(rtwdev, 0xb58, BIT(0));
rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA);
rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA);
rtw_write32_clr(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION);
rtw_write32_clr(rtwdev, 0x1830, BIT(30));
rtw_write32_clr(rtwdev, 0x4130, BIT(30));
rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
rtw_write32_clr(rtwdev, REG_CCA2ND, BIT(3));
rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, BIT(15));
rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
rtw_write32_clr(rtwdev, REG_RXPKT_NUM, BIT_RW_RELEASE);