rtw_write32_set
rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER);
rtw_write32_set(rtwdev, REG_DWBCN0_CTRL, BIT_BCN_VALID);
rtw_write32_set(rtwdev, REG_RCR, BIT_DISGCLK);
rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT);
rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS);
rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS);
rtw_write32_set(rtwdev, REG_FWHW_TXQ_CTRL,
rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_HGQMD);
rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
rtw_write32_set(rtwdev, RTK_PCI_TXBD_H2CQ_CSR,
rtw_write32_set(rtwdev, RTK_PCI_CTRL,
rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN);
rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN);
rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4);
rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
rtw_write32_set(rtwdev, REG_CCASEL, BIT(31));
rtw_write32_set(rtwdev, REG_CCASEL, BIT(31));
rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
rtw_write32_set(rtwdev, REG_FAS, BIT(17));
rtw_write32_set(rtwdev, REG_CCK0_FAREPORT, BIT(15));
rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
rtw_write32_set(rtwdev, REG_CCK_RPT_FORMAT, BIT(2));
rtw_write32_set(rtwdev, REG_PRECTRL, BIT_IQ_WGT);
rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST);
rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN);
rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
rtw_write32_set(rtwdev, REG_FAS, BIT(17));
rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
rtw_write32_set(rtwdev, 0x9a4, BIT(17));
rtw_write32_set(rtwdev, 0xa2c, BIT(15));
rtw_write32_set(rtwdev, 0xb58, BIT(0));
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN);
rtw_write32_set(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION);
rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN);
rtw_write32_set(rtwdev, 0x1830, BIT(30));
rtw_write32_set(rtwdev, 0x4130, BIT(30));
rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
rtw_write32_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
rtw_write32_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(12));
rtw_write32_set(rtwdev, REG_CCA2ND, BIT(3));
rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
rtw_write32_set(rtwdev, REG_FAS, BIT(17));
rtw_write32_set(rtwdev, REG_CCK0_FAREPORT, BIT(15));
rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
rtw_write32_set(rtwdev, REG_FPGA0_XCD_RF_PARA, BIT(6));
rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
rtw_write32_set(rtwdev, REG_RXDMA_AGG_PG_TH, BIT_EN_PRE_CALC);
rtw_write32_set(rtwdev, REG_PAD_CTRL2, BIT_NO_PDN_CHIPOFF_V1);
rtw_write32_set(rtwdev, REG_RXPKT_NUM, BIT_RW_RELEASE);