rtw_read32_mask
rtw_read32_mask(rtwdev, reg->addr, reg->mask));
rtw_read32_mask(rtwdev, edcca_th[EDCCA_TH_L2H_IDX].hw_reg.addr,
rtw_read32_mask(rtwdev, edcca_th[EDCCA_TH_H2L_IDX].hw_reg.addr,
rtw_read32_mask(rtwdev, REG_EDCCA_REPORT, BIT_EDCCA_FLAG) ?
val = rtw_read32_mask(rtwdev, reg->addr, reg->mask);
v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask);
v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask);
wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG,
en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8));
val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK);
dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
val = rtw_read32_mask(rtwdev, direct_addr, mask);
if (rtw_read32_mask(rtwdev, REG_TCR, BIT_PWRMGT_HWDATA_EN) == 0)
tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL);
tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL);
rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
rtw_read32_mask(rtwdev, REG_IQK_RES_TX,
rtw_read32_mask(rtwdev, REG_IQK_RES_TY,
rtw_read32_mask(rtwdev, REG_IQK_RES_RX,
rtw_read32_mask(rtwdev, REG_IQK_RES_RY,
oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) {
tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL);
tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL);
rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
oldval_0 = rtw_read32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0);
rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0);
cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8;
backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0);
backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0);
rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
rtw_read32_mask(rtwdev, REG_IQC_X, 0x000007ff),
rtw_read32_mask(rtwdev, REG_IQC_Y, 0x000007ff));
rtw_read32_mask(rtwdev, REG_IQKXB, 0x000007ff),
rtw_read32_mask(rtwdev, REG_IQKYB, 0x000007ff));
iqk0_ready = rtw_read32_mask(rtwdev,
iqk1_ready = rtw_read32_mask(rtwdev,
tx0_fail = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(12));
tx1_fail = rtw_read32_mask(rtwdev, REG_IQKB_END, BIT(12));
tx_x0_temp[tx0_avg] = rtw_read32_mask(rtwdev,
tx_y0_temp[tx0_avg] = rtw_read32_mask(rtwdev,
tx_x1_temp[tx1_avg] = rtw_read32_mask(rtwdev,
tx_y1_temp[tx1_avg] = rtw_read32_mask(rtwdev,
iqk0_ready = rtw_read32_mask(rtwdev,
iqk1_ready = rtw_read32_mask(rtwdev,
rx0_fail = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(11));
rx1_fail = rtw_read32_mask(rtwdev, REG_IQKB_END, BIT(11));
rx_x0_temp[rx0_avg] = rtw_read32_mask(rtwdev,
rx_y0_temp[rx0_avg] = rtw_read32_mask(rtwdev,
rx_x1_temp[rx1_avg] = rtw_read32_mask(rtwdev,
rx_y1_temp[rx1_avg] = rtw_read32_mask(rtwdev,
cont_tx = rtw_read32_mask(rtwdev, REG_SINGLE_TONE_CONT_TX, 0x70000);
if (read_poll_timeout(!rtw_read32_mask, lok_ready, lok_ready,
lok_temp2 = rtw_read32_mask(rtwdev, 0x1bfc, 0x003e0000);
lok_temp1 = rtw_read32_mask(rtwdev, 0x1bfc, 0x0000003e);
if (read_poll_timeout(!rtw_read32_mask, *tx_ok, *tx_ok,
*tx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26));
if (read_poll_timeout(!rtw_read32_mask, rx_ok, rx_ok,
rx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26));
iqk_ready = rtw_read32_mask(rtwdev,
tx_fail = rtw_read32_mask(rtwdev,
vdf_x[k] = rtw_read32_mask(rtwdev,
vdf_y[k] = rtw_read32_mask(rtwdev,
iqk_ready = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(10));
tx_fail = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(12));
tx_x0[cal] = rtw_read32_mask(rtwdev, REG_IQKA_END,
tx_y0[cal] = rtw_read32_mask(rtwdev, REG_IQKA_END,
iqk_ready = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(10));
rx_fail = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(11));
rx_x0[cal] = rtw_read32_mask(rtwdev, REG_IQKA_END,
rx_y0[cal] = rtw_read32_mask(rtwdev, REG_IQKA_END,
swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000);
igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
ret = read_poll_timeout(rtw_read32_mask, u4b_tmp,
read_poll_timeout(rtw_read32_mask, val,
cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD);
i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26));
tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN);
pd = rtw_read32_mask(rtwdev,
cs = rtw_read32_mask(rtwdev,
nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
efuse->btcoex = rtw_read32_mask(rtwdev, REG_WL_BT_PWR_CTRL,
hal->cck_high_power = rtw_read32_mask(rtwdev, REG_CCK_RPT_FORMAT,
pi_mode = rtw_read32_mask(rtwdev, pi_addr[rf_path], 0x4);
val = rtw_read32_mask(rtwdev, read_addr[pi_mode][rf_path], mask);
efuse->btcoex = rtw_read32_mask(rtwdev, REG_WL_BT_PWR_CTRL,
if (!rtw_read32_mask(rtwdev, REG_LLT_INIT, BIT(31) | BIT(30)))
if (rtw_read32_mask(rtwdev, addr, mask) == target)
if (!rtw_read32_mask(rtwdev, REG_BCNQ_INFO, BIT_MGQ_CPU_EMPTY))
ret = read_poll_timeout(rtw_read32_mask, check_dis,
ret = read_poll_timeout(rtw_read32_mask, check_dis,