rtw89_write8
rtw89_write8(rtwdev, addr, val | bit);
rtw89_write8(rtwdev, addr, val & ~bit);
rtw89_write8(rtwdev, addr, set);
rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8);
rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8);
rtw89_write8(rtwdev, addr, (u8)val);
rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8 & ~B_AX_TMAC_EN);
rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8);
rtw89_write8(rtwdev, chip->h2c_ctrl_reg, B_AX_H2CREG_TRIGGER);
rtw89_write8(rtwdev, chip->c2h_ctrl_reg, 0);
rtw89_write8(rtwdev, addr, val);
rtw89_write8(rtwdev, reg + 3, val);
rtw89_write8(rtwdev, R_AX_SS_CTRL, val);
rtw89_write8(rtwdev, reg, win);
rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);
rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);
rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);
rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY);
rtw89_write8(rtwdev, reg, val8);
rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY);
rtw89_write8(rtwdev, R_AX_MDIO_CFG, addr & 0x1F);
rtw89_write8(rtwdev, R_AX_DBI_WDATA + addr_2lsb, data);
rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_WFLAG >> 16);
rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_RFLAG >> 16);
rtw89_write8(rtwdev, addr + phy->cr_base, data);
rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
rtw89_write8(rtwdev, R_AX_RXDMA_SETTING, USB3_BULKSIZE);
rtw89_write8(rtwdev, R_AX_RXDMA_SETTING, USB2_BULKSIZE);
rtw89_write8(rtwdev, R_AX_RXDMA_SETTING, USB11_BULKSIZE);
rtw89_write8(rtwdev, info->usb_endpoint_2 + 1, NUMP);