drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

334

uint32_t scl_mode = REG_READ(SCL_MODE);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

364

scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

368

REG_SET_2(SCL_MODE, scl_mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

95

dpp_reg_state->scl_mode = REG_READ(SCL_MODE);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

338

uint32_t scl_mode = REG_READ(SCL_MODE);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

368

scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

372

REG_SET_2(SCL_MODE, scl_mode,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

210

uint32_t scl_mode;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

759

static enum scl_mode spl_get_dscl_mode(const struct spl_in *spl_in,