rtw89_read8
val = rtw89_read8(rtwdev, addr);
val = rtw89_read8(rtwdev, addr);
orig = rtw89_read8(rtwdev, addr);
orig = rtw89_read8(rtwdev, addr);
val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL);
val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
data = rtw89_read8(rtwdev, addr);
val8 = rtw89_read8(rtwdev, R_AX_CMAC_FUNC_EN);
cnt->l0_sim = rtw89_read8(rtwdev, R_BE_SER_L0_DBG_CNT1 + 3);
ret = read_poll_timeout(rtw89_read8, val, val == 0, 1000, 5000, false,
ret = read_poll_timeout_atomic(rtw89_read8, val, val, 1,
ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk),
val = rtw89_read8(rtwdev, addr);
val = rtw89_read8(rtwdev, R_AX_SS_CTRL);
ret = read_poll_timeout(rtw89_read8, val,
val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);
val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);
val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL);
return read_poll_timeout_atomic(rtw89_read8, val, val & check,
ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
val8 = rtw89_read8(rtwdev, reg);
ret = read_poll_timeout_atomic(rtw89_read8, val8, !(val8 & B_BE_PTCL_BUSY),
ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10,
ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10,
*value = rtw89_read8(rtwdev, read_addr);
return rtw89_read8(rtwdev, addr + phy->cr_base);
reason = rtw89_read8(rtwdev, wow_reason_reg);