rtw89_phy_write32_set
rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
rtw89_phy_write32_set(rtwdev, addr, bits);
rtw89_phy_write32_set(rtwdev, regs->r1b_rx_rpt_rst.addr,
rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);
rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON);
rtw89_phy_write32_set(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON);
rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON);
rtw89_phy_write32_set(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON);
rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET);
rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN);
rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON);
rtw89_phy_write32_set(rtwdev, R_S0_RXDC2 + (path << 13), B_S0_RXDC2_MEN);
rtw89_phy_write32_set(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST);
rtw89_phy_write32_set(rtwdev, addr, BIT(30));
rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN);
rtw89_phy_write32_set(rtwdev, R_S0_RXDC2, B_S0_RXDC2_MEN);
rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
rtw89_phy_write32_set(rtwdev, R_S1_RXDC2, B_S1_RXDC2_EN);
rtw89_phy_write32_set(rtwdev, R_S0_DACKI, B_S0_DACKI_EN);
rtw89_phy_write32_set(rtwdev, R_S0_DACKQ, B_S0_DACKQ_EN);
rtw89_phy_write32_set(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG);
rtw89_phy_write32_set(rtwdev, R_S1_DACKI, B_S1_DACKI_EN);
rtw89_phy_write32_set(rtwdev, R_S1_DACKQ, B_S1_DACKQ_EN);
rtw89_phy_write32_set(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON);
rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN);
rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET);
rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET);
rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN);
rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN);
rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN);
rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A);
rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT,
rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2,
rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN);
rtw89_phy_write32_set(rtwdev, R_P0_DAC_COMP_POST_DPD_EN,
rtw89_phy_write32_set(rtwdev, R_P1_DAC_COMP_POST_DPD_EN,
rtw89_phy_write32_set(rtwdev, addr, BIT(0));
rtw89_phy_write32_set(rtwdev, R_BBCLK, B_CLK_640M);
rtw89_phy_write32_set(rtwdev, R_USED_TSSI_TRK_ON_P0_BE4 + addr_ofst,