sca_out
sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port);
sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);
sca_out(rxs, MSCI1_OFFSET + RXS, port);
sca_out(txs, MSCI1_OFFSET + TXS, port);
sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
sca_out(0, transmit ? DSR_TX(phy_node(port)) :
sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
sca_out(0, dmac + CPB, card); /* pointer base */
sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
sca_out(0x14, DMR_RX(phy_node(port)), card);
sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
sca_out(0x14, DMR_TX(phy_node(port)), card);
sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
sca_out(port->tmc, msci + TMC, card);
sca_out(port->rxs, msci + RXS, card);
sca_out(port->txs, msci + TXS, card);
sca_out(md2, msci + MD2, card);
sca_out(CMD_RESET, msci + CMD, card);
sca_out(md0, msci + MD0, card);
sca_out(0x00, msci + MD1, card); /* no address field check */
sca_out(md2, msci + MD2, card);
sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
sca_out(CTL_IDLE, msci + CTL, card);
sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
sca_out(port->tmc, msci + TMC, card); /* Restore registers */
sca_out(port->rxs, msci + RXS, card);
sca_out(port->txs, msci + TXS, card);
sca_out(CMD_TX_ENABLE, msci + CMD, card);
sca_out(CMD_RX_ENABLE, msci + CMD, card);
sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
sca_out(wait_states, WCRL, card); /* Wait Control */
sca_out(wait_states, WCRM, card);
sca_out(wait_states, WCRH, card);
sca_out(0, DMER, card); /* DMA Master disable */
sca_out(0x03, PCR, card); /* DMA priority */
sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
sca_out(0, DSR_TX(0), card);
sca_out(0, DSR_RX(1), card);
sca_out(0, DSR_TX(1), card);
sca_out(DMER_DME, DMER, card); /* DMA Master enable */
sca_out(0, DSR_RX(port->chan), card);
sca_out(0, DSR_TX(port->chan), card);
sca_out(DCR_ABORT, DCR_RX(port->chan), card);
sca_out(DCR_ABORT, DCR_TX(port->chan), card);
sca_out(DCR_CLEAR_EOF, DCR_RX(port->chan), card);
sca_out(DCR_CLEAR_EOF, DCR_TX(port->chan), card);
sca_out(0x14, DMR_RX(port->chan), card); /* Chain mode, Multi-frame */
sca_out(DIR_EOME, DIR_RX(port->chan), card); /* enable interrupts */
sca_out(DSR_DE, DSR_RX(port->chan), card); /* DMA enable */
sca_out(0x14, DMR_TX(port->chan), card); /* Chain mode, Multi-frame */
sca_out(DIR_EOME, DIR_TX(port->chan), card); /* enable interrupts */
sca_out(ST1_CDCD, msci + ST1, card);
sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
sca_out(DSR_DE, DSR_RX(port->chan), card);
sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
sca_out(port->tmc, msci + TMCR, card);
sca_out(port->tmc, msci + TMCT, card);
sca_out(port->rxs, msci + RXS, card);
sca_out(port->txs, msci + TXS, card);
sca_out(md2, msci + MD2, card);
sca_out(CMD_RESET, msci + CMD, card);
sca_out(md0, msci + MD0, card);
sca_out(0x00, msci + MD1, card); /* no address field check */
sca_out(md2, msci + MD2, card);
sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
sca_out(port->tmc, msci + TMCR, card);
sca_out(port->tmc, msci + TMCT, card);
sca_out(port->rxs, msci + RXS, card);
sca_out(port->txs, msci + TXS, card);
sca_out(CMD_TX_ENABLE, msci + CMD, card);
sca_out(CMD_RX_ENABLE, msci + CMD, card);
sca_out(CMD_RESET, get_msci(port) + CMD, port->card);
sca_out(DSR_DE, DSR_TX(port->chan), card); /* Enable TX DMA */
sca_out(wait_states, WCRL, card); /* Wait Control */
sca_out(wait_states, WCRM, card);
sca_out(wait_states, WCRH, card);
sca_out(0, DMER, card); /* DMA Master disable */
sca_out(0x03, PCR, card); /* DMA priority */
sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
sca_out(0, DSR_TX(0), card);
sca_out(0, DSR_RX(1), card);
sca_out(0, DSR_TX(1), card);
sca_out(DMER_DME, DMER, card); /* DMA Master enable */
sca_out(rxs, msci + RXS, card);
sca_out(txs, msci + TXS, card);
sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
sca_out(rxs, msci + RXS, card);
sca_out(txs, msci + TXS, card);
sca_out(0x10, BTCR, card);
sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
sca_out(rxs, msci + RXS, card);
sca_out(txs, msci + TXS, card);