sbus_writeb
sbus_writeb(value, &sun_fdc->dor_82077);
sbus_writeb(value, &sun_fdc->data_82077);
sbus_writeb(value, &sun_fdc->dcr_82077);
sbus_writeb(value, &sun_fdc->status_82077);
sbus_writeb(tmp, d);
sbus_writeb(c, __dst);
sbus_writeb(c, dst);
sbus_writeb(tmp, d);
#define apc_writeb(val, offs) (sbus_writeb(val, regs+offs))
sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M,
sbus_writeb(newval, auxio_register);
#define pmc_writeb(val, offs) (sbus_writeb(val, regs+offs))
sbus_writeb(power_register, auxio_power_register);
sbus_writeb(0x00, info->regs + 0);
sbus_writeb(sbus_readb(info->enable_reg) | 3, info->enable_reg);
sbus_writeb(0xB6, info->freq_regs + 1);
sbus_writeb(count & 0xff, info->freq_regs + 0);
sbus_writeb((count >> 8) & 0xff, info->freq_regs + 0);
sbus_writeb(sbus_readb(info->enable_reg) & 0xFC, info->enable_reg);
sbus_writeb(0x01, info->regs + 0);
sbus_writeb(0x00, info->regs + 2);
sbus_writeb((count >> 16) & 0xff, info->regs + 3);
sbus_writeb((count >> 8) & 0xff, info->regs + 4);
sbus_writeb(0x00, info->regs + 5);
sbus_writeb(src[0], piobuf);
sbus_writeb(0, piobuf);
sbus_writeb(0, piobuf);
sbus_writeb(0, piobuf);
sbus_writeb(LE_T1_POK | LE_T1_OWN, &ib->btx_ring[entry].tmd1_bits);
sbus_writeb(dev->dev_addr[1], &ib->phys_addr[0]);
sbus_writeb(dev->dev_addr[0], &ib->phys_addr[1]);
sbus_writeb(dev->dev_addr[3], &ib->phys_addr[2]);
sbus_writeb(dev->dev_addr[2], &ib->phys_addr[3]);
sbus_writeb(dev->dev_addr[5], &ib->phys_addr[4]);
sbus_writeb(dev->dev_addr[4], &ib->phys_addr[5]);
sbus_writeb(leptr >> 16,&ib->btx_ring [i].tmd1_hadr);
sbus_writeb(0, &ib->btx_ring [i].tmd1_bits);
sbus_writeb(leptr >> 16,&ib->brx_ring [i].rmd1_hadr);
sbus_writeb(LE_R1_OWN, &ib->brx_ring [i].rmd1_bits);
sbus_writeb(LE_R1_OWN, &rd->rmd1_bits);
sbus_writeb(LE_R1_OWN, &rd->rmd1_bits);
sbus_writeb(bits & ~(LE_T1_POK), &td->tmd1_bits);
sbus_writeb(dev->dev_addr[i], ð->h_dest[i]);
sbus_writeb(dev->dev_addr[i], ð->h_source[i]);
sbus_writeb(LE_T1_POK|LE_T1_OWN, &ib->btx_ring[entry].tmd1_bits);
sbus_writeb(MREGS_PHYCONFIG_AUTO, mregs + MREGS_PHYCONFIG);
sbus_writeb(MREGS_TXFCNTL_AUTOPAD, mregs + MREGS_TXFCNTL);
sbus_writeb(0, mregs + MREGS_RXFCNTL);
sbus_writeb(MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ, mregs + MREGS_IMASK);
sbus_writeb(MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS, mregs + MREGS_BCONFIG);
sbus_writeb((MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 |
sbus_writeb(MREGS_PLSCONFIG_TP, mregs + MREGS_PLSCONFIG);
sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET,
sbus_writeb(e[0], mregs + MREGS_ETHADDR);
sbus_writeb(e[1], mregs + MREGS_ETHADDR);
sbus_writeb(e[2], mregs + MREGS_ETHADDR);
sbus_writeb(e[3], mregs + MREGS_ETHADDR);
sbus_writeb(e[4], mregs + MREGS_ETHADDR);
sbus_writeb(e[5], mregs + MREGS_ETHADDR);
sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
sbus_writeb(0, mregs + MREGS_FILTER);
sbus_writeb(0, mregs + MREGS_IACONFIG);
sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
sbus_writeb(0xff, qep->mregs + MREGS_FILTER);
sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
sbus_writeb(tmp, qep->mregs + MREGS_FILTER);
sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG);
sbus_writeb(MREGS_BCONFIG_RESET, mregs + MREGS_BCONFIG);
sbus_writeb(value_or, ®s->p_or);
sbus_writeb(value_tcr, ®s->p_tcr);
sbus_writeb(value_tcr, ®s->p_tcr);
sbus_writeb(val, ®s->p_tcr);
sbus_writeb(value_tcr, ®s->p_tcr);
sbus_writeb(d, ®s->p_dr);
sbus_writeb(val, esp->regs + (reg * 4UL));
#define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
#define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
sbus_writeb(val, ®s->control);
sbus_writeb(val, ®s->control);
sbus_writeb(p[1], regp);
sbus_writeb(val, ®s->mcr);
sbus_writeb(cur_mode, ®s->mcr);
sbus_writeb(val, ®s->control);
sbus_writeb(val, ®s->control);
sbus_writeb(p[1], regp);
sbus_writeb(p[0], regp);
sbus_writeb(p[1], regp);
sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
sbus_writeb(0, amd->regs + AMD7930_DR);
sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR);
sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR);
sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR);
sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR);
sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR);
sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR);
sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR);
sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR);
sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR);
sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR);
sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR);
sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR);
sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR);
sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR);
sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR);
sbus_writeb(map->mmr1, amd->regs + AMD7930_DR);
sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR);
sbus_writeb(map->mmr2, amd->regs + AMD7930_DR);
sbus_writeb(byte, amd->regs + AMD7930_BBTB);
sbus_writeb(0, amd->regs + AMD7930_BBTB);
sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR);
sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
sbus_writeb(0, amd->regs + AMD7930_DR);
sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR);
sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4),
return sbus_writeb(val, reg_addr);