sbus_readl
sbus_readl(&sun4d_timers->l10_timer_limit);
sbus_readl(&timers_global->l10_limit);
si = sbus_readl(&sun4m_irq_global->pending);
sbus_readl(&timers_percpu[cpu]->l14_limit);
val = sbus_readl(master_l10_counter);
control = sbus_readl(&iommu->regs->control);
return sbus_readl(addr);
csr = sbus_readl(lp->dregs + DMA_CSR);
u32 csr = sbus_readl(lp->dregs + DMA_CSR);
while (sbus_readl(lp->dregs + DMA_CSR) & DMA_FIFO_ISDRAIN)
csr = sbus_readl(lp->dregs + DMA_CSR);
printk("dcsr=%8.8x\n", sbus_readl(lp->dregs + DMA_CSR));
u32 csr = sbus_readl(lp->dregs + DMA_CSR);
*p32++ = sbus_readl(pbuf);
u32 addr = sbus_readl(lp->dregs + DMA_ADDR);
u32 dma_csr = sbus_readl(lp->dregs + DMA_CSR);
csr = sbus_readl(lp->dregs + DMA_CSR);
tmp = sbus_readl(bregs + BMAC_RXCFG);
while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
tmp = sbus_readl(bregs + BMAC_RXCFG);
tmp = sbus_readl(bregs + BMAC_RXCFG);
if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
sbus_readl(bregs + BMAC_TXCFG));
while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
sbus_readl(bregs + BMAC_RXCFG));
stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
(sbus_readl(bregs + BMAC_EXCTR) +
sbus_readl(bregs + BMAC_LTCTR));
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
sbus_readl(tregs + TCVR_MPAL);
retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_MPAL);
mpal = sbus_readl(tregs + TCVR_MPAL);
sbus_readl(tregs + TCVR_TPAL);
sbus_readl(tregs + TCVR_TPAL);
sbus_readl(tregs + TCVR_MPAL),
sbus_readl(tregs + TCVR_TPAL));
sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
bmac_status = sbus_readl(bp->creg + CREG_STAT);
qec_status = sbus_readl(bp->gregs + GLOB_STAT);
return sbus_readl(reg);
sbus_readl(__reg)
u32 tmp = sbus_readl(cregs + CREG_CTRL);
tmp = qep->channel * sbus_readl(gregs + GLOB_MSIZE);
tmp = sbus_readl(cregs + CREG_RXRBUFPTR) +
sbus_readl(gregs + GLOB_RSIZE);
qec_status = sbus_readl(qecp->gregs + GLOB_STAT);
qe_status = sbus_readl(qep->qcregs + CREG_STAT);
u32 tmp = sbus_readl(gregs + GLOB_CTRL);
ctrl = sbus_readl(qecp->gregs + GLOB_CTRL);
tmp = sbus_readl(®s->p_csr);
tmp = sbus_readl(®s->p_csr);
if (UCTRL_STAT_TXNF_STA & sbus_readl(&driver->regs->uctrl_stat)) \
if ((UCTRL_STAT_RXNE_STA & sbus_readl(&driver->regs->uctrl_stat)) == 0) \
value = sbus_readl(&driver->regs->uctrl_data); \
stat = sbus_readl(&driver->regs->uctrl_stat);
intr = sbus_readl(&driver->regs->uctrl_intr);
sbus_readl(esp->dma_regs + (REG))
if (!(sbus_readl(&fbc->s) & 0x10000000))
val = sbus_readl(&fbc->draw);
i = sbus_readl(&fbc->blit);
val = sbus_readl(&thc->thc_misc);
conf = sbus_readl(par->fhc);
rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK;
conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) |
mode = sbus_readl(&fbc->mode);
i = sbus_readl(&fbc->s);
(sbus_readl(&lx_krn->krn_csr) & LEO_KRN_CSR_PROGRESS) &&
val = sbus_readl(&par->lc_ss0_usr->csr);
sbus_writel(sbus_readl(&cursor->cur_misc) & ~LEO_CUR_ENABLE, &cursor->cur_misc);
val = sbus_readl(&lx_krn->krn_csr);
val = sbus_readl(&lx_krn->krn_csr);
val = sbus_readl(&lx_krn->krn_csr);
val = sbus_readl(&lx_krn->krn_csr);
val = sbus_readl(&par->ld_ss1->ss1_misc);
val = sbus_readl(®s->vid_screenpaint_timectl1);
val = sbus_readl(®s->vid_screenpaint_timectl1);
u32 tmp = sbus_readl(p);
val = sbus_readl(&thc->thc_misc);
csr = sbus_readl(chip->port + APCCSR);
csr = sbus_readl(base->regs + APCCSR);
csr = sbus_readl(base->regs + APCCSR);
csr = sbus_readl(base->regs + APCCSR);
return sbus_readl(base->regs + base->dir + APCVA);
tmp = sbus_readl(dbri->regs + REG0);
tmp = sbus_readl(dbri->regs + REG0);
tmp = sbus_readl(dbri->regs + REG0);
tmp = sbus_readl(dbri->regs + REG0);
u32 reg2 = sbus_readl(dbri->regs + REG2);
x = sbus_readl(dbri->regs + REG1);
tmp = sbus_readl(dbri->regs + REG0);
snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr)
tmp = sbus_readl(dbri->regs + REG0);
sbus_readl(dbri->regs + REG0),
sbus_readl(dbri->regs + REG2),
sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
tmp = sbus_readl(dbri->regs + REG0);