drivers/gpu/drm/vc4/vc4_crtc.c

1495

CRTC_WRITE(PV_INTEN, 0);

drivers/gpu/drm/vc4/vc4_crtc.c

1496

CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);

drivers/gpu/drm/vc4/vc4_crtc.c

1515

CRTC_WRITE(PV_INTEN, 0);

drivers/gpu/drm/vc4/vc4_crtc.c

339

CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);

drivers/gpu/drm/vc4/vc4_crtc.c

340

CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);

drivers/gpu/drm/vc4/vc4_crtc.c

385

CRTC_WRITE(PV_HORZA,

drivers/gpu/drm/vc4/vc4_crtc.c

391

CRTC_WRITE(PV_HORZB,

drivers/gpu/drm/vc4/vc4_crtc.c

417

CRTC_WRITE(PV_VERTA_EVEN,

drivers/gpu/drm/vc4/vc4_crtc.c

420

CRTC_WRITE(PV_VERTB_EVEN,

drivers/gpu/drm/vc4/vc4_crtc.c

427

CRTC_WRITE(PV_V_CONTROL,

drivers/gpu/drm/vc4/vc4_crtc.c

436

CRTC_WRITE(PV_VSYNCD_EVEN,

drivers/gpu/drm/vc4/vc4_crtc.c

439

CRTC_WRITE(PV_V_CONTROL,

drivers/gpu/drm/vc4/vc4_crtc.c

443

CRTC_WRITE(PV_VSYNCD_EVEN, 0);

drivers/gpu/drm/vc4/vc4_crtc.c

446

CRTC_WRITE(PV_VERTA,

drivers/gpu/drm/vc4/vc4_crtc.c

449

CRTC_WRITE(PV_VERTB,

drivers/gpu/drm/vc4/vc4_crtc.c

454

CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);

drivers/gpu/drm/vc4/vc4_crtc.c

457

CRTC_WRITE(PV_MUX_CFG,

drivers/gpu/drm/vc4/vc4_crtc.c

462

CRTC_WRITE(PV_PIPE_INIT_CTRL,

drivers/gpu/drm/vc4/vc4_crtc.c

467

CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |

drivers/gpu/drm/vc4/vc4_crtc.c

512

CRTC_WRITE(PV_V_CONTROL,

drivers/gpu/drm/vc4/vc4_crtc.c

681

CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);

drivers/gpu/drm/vc4/vc4_crtc.c

689

CRTC_WRITE(PV_V_CONTROL,

drivers/gpu/drm/vc4/vc4_crtc.c

801

CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);

drivers/gpu/drm/vc4/vc4_crtc.c

817

CRTC_WRITE(PV_INTEN, 0);

drivers/gpu/drm/vc4/vc4_crtc.c

874

CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);