drivers/gpu/drm/vc4/vc4_crtc.c

339

CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);

drivers/gpu/drm/vc4/vc4_crtc.c

340

CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);

drivers/gpu/drm/vc4/vc4_crtc.c

513

CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);

drivers/gpu/drm/vc4/vc4_crtc.c

514

ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);

drivers/gpu/drm/vc4/vc4_crtc.c

572

if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))

drivers/gpu/drm/vc4/vc4_crtc.c

575

if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))

drivers/gpu/drm/vc4/vc4_crtc.c

582

encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);

drivers/gpu/drm/vc4/vc4_crtc.c

681

CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);

drivers/gpu/drm/vc4/vc4_crtc.c

690

CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);

drivers/gpu/drm/vc4/vc4_crtc.c

870

u32 stat = CRTC_READ(PV_INTSTAT);