rtl8xxxu_write32_set
rtl8xxxu_write32_set(priv, REG_FPGA0_XCD_RF_PARM, FPGA0_RF_PARM_CLK_GATE);
rtl8xxxu_write32_set(priv, REG_FPGA0_XCD_RF_PARM, BIT(31));
rtl8xxxu_write32_set(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x70000);
rtl8xxxu_write32_set(priv, REG_PAD_CTRL1, BIT(29) | BIT(28));
rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET);
rtl8xxxu_write32_set(priv, REG_AFE_MISC, BIT(18));
rtl8xxxu_write32_set(priv, REG_LDO_SW_CTRL, BIT(31));
rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET);
rtl8xxxu_write32_set(priv, REG_GPIO_INTM, BIT(16));
rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_CCK);
rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM);
int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits);