s5h1420_writereg
s5h1420_writereg(state, 0x3c,
s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
s5h1420_writereg(state, 0x3b,
s5h1420_writereg(state, 0x3b,
s5h1420_writereg(state, 0x3b, 0x02);
s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
s5h1420_writereg(state, 0x3b, val);
s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
s5h1420_writereg(state, 0x3b, val);
s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
s5h1420_writereg(state, 0x3b, val);
s5h1420_writereg(state, Vit09, 0x13);
s5h1420_writereg(state, Vit09, 0x1b);
s5h1420_writereg(state, FEC01, 0x18);
s5h1420_writereg(state, FEC01, 0x10);
s5h1420_writereg(state, FEC01, val);
s5h1420_writereg(state, Mpeg02, val | (1 << 6));
s5h1420_writereg(state, QPSK01, val);
s5h1420_writereg(state, Loop04, 0x8a);
s5h1420_writereg(state, Loop05, 0x6a);
s5h1420_writereg(state, Loop04, 0x58);
s5h1420_writereg(state, Loop05, 0x27);
s5h1420_writereg(state, 0x46, 0x1d);
s5h1420_writereg(state, 0x46, 0x1f);
s5h1420_writereg (state, 0x01, 0x08);
s5h1420_writereg (state, 0x01, 0x00);
s5h1420_writereg(state, Loop01, v & 0x7f);
s5h1420_writereg(state, Tnco01, val >> 16);
s5h1420_writereg(state, Tnco02, val >> 8);
s5h1420_writereg(state, Tnco03, val & 0xff);
s5h1420_writereg(state, Loop01, v | 0x80);
s5h1420_writereg(state, Loop01, v & 0xbf);
s5h1420_writereg(state, Pnco01, val >> 16);
s5h1420_writereg(state, Pnco02, val >> 8);
s5h1420_writereg(state, Pnco03, val & 0xff);
s5h1420_writereg(state, Loop01, v | 0x40);
s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
s5h1420_writereg(state, Vit08, vit08);
s5h1420_writereg(state, Vit09, vit09);
s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
s5h1420_writereg(state, PLL02, 0x40);
s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
s5h1420_writereg(state, QPSK01, 0xae | 0x10);
s5h1420_writereg(state, QPSK01, 0xac | 0x10);
s5h1420_writereg(state, CON_1, 0x00);
s5h1420_writereg(state, QPSK02, 0x00);
s5h1420_writereg(state, Pre01, 0xb0);
s5h1420_writereg(state, Loop01, 0xF0);
s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
s5h1420_writereg(state, Loop04, 0x79);
s5h1420_writereg(state, Loop04, 0x58);
s5h1420_writereg(state, Loop05, 0x6b);
s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
s5h1420_writereg(state, Sync01, 0x33);
s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
s5h1420_writereg(state, DiS03, 0x00);
s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
s5h1420_writereg(state, 0x02, state->CON_1_val);
return s5h1420_writereg(state, 0x02, state->CON_1_val);