arch/mips/include/asm/mach-ralink/mt7620.h

62

return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;

arch/mips/include/asm/mach-ralink/ralink_regs.h

47

u32 val = rt_sysc_r32(reg) & ~clr;

arch/mips/pci/pci-mt7620.c

248

if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {

arch/mips/pci/pci-mt7620.c

271

if (rt_sysc_r32(RALINK_SYSCFG0) & RALINK_SYSCFG0_XTAL40) {

arch/mips/pci/pci-rt3883.c

307

rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);

arch/mips/pci/pci-rt3883.c

308

syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);

arch/mips/pci/pci-rt3883.c

309

clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);

arch/mips/pci/pci-rt3883.c

320

t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);

arch/mips/pci/pci-rt3883.c

324

t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);

arch/mips/pci/pci-rt3883.c

328

t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);

arch/mips/pci/pci-rt3883.c

332

t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);

arch/mips/pci/pci-rt3883.c

382

t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);

arch/mips/pci/pci-rt3883.c

389

t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);

arch/mips/pci/pci-rt3883.c

393

t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);

drivers/pinctrl/mediatek/pinctrl-mtmips.c

141

mode = rt_sysc_r32(reg);

drivers/watchdog/rt2880_wdt.c

120

if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)