rzn1_adc
static int rzn1_adc_power(struct rzn1_adc *rzn1_adc, bool power)
rzn1_adc->regs + RZN1_ADC_CONFIG_REG);
return readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_CONTROL_REG,
static void rzn1_adc_vc_setup_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
writel(vc, rzn1_adc->regs + RZN1_ADC_VC_REG(ch));
static int rzn1_adc_vc_start_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
val = readl(rzn1_adc->regs + RZN1_ADC_FORCE_REG);
writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_SET_FORCE_REG);
static void rzn1_adc_vc_stop_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_CLEAR_FORCE_REG);
static int rzn1_adc_vc_wait_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
ret = readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_FORCE_REG,
data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC1_DATA_REG(ch));
data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC2_DATA_REG(ch));
static int rzn1_adc_read_raw_ch(struct rzn1_adc *rzn1_adc, unsigned int chan, int *val)
ACQUIRE(pm_runtime_active_auto_try_enabled, pm)(rzn1_adc->dev);
scoped_guard(mutex, &rzn1_adc->lock) {
rzn1_adc_vc_setup_conversion(rzn1_adc, chan, adc1_ch, adc2_ch);
ret = rzn1_adc_vc_start_conversion(rzn1_adc, chan);
ret = rzn1_adc_vc_wait_conversion(rzn1_adc, chan, adc1_data, adc2_data);
rzn1_adc_vc_stop_conversion(rzn1_adc, chan);
static int rzn1_adc_get_vref_mV(struct rzn1_adc *rzn1_adc, unsigned int chan)
return rzn1_adc->adc1_vref_mV;
return rzn1_adc->adc2_vref_mV;
struct rzn1_adc *rzn1_adc = iio_priv(indio_dev);
ret = rzn1_adc_read_raw_ch(rzn1_adc, chan->channel, val);
ret = rzn1_adc_get_vref_mV(rzn1_adc, chan->channel);
static int rzn1_adc_set_iio_dev_channels(struct rzn1_adc *rzn1_adc,
if (rzn1_adc->adc1_vref_mV >= 0) {
if (rzn1_adc->adc2_vref_mV >= 0) {
if (rzn1_adc->adc2_vref_mV >= 0) {
return dev_err_probe(rzn1_adc->dev, -ENODEV,
static int rzn1_adc_core_get_regulators(struct rzn1_adc *rzn1_adc,
struct device *dev = rzn1_adc->dev;
struct rzn1_adc *rzn1_adc;
indio_dev = devm_iio_device_alloc(dev, sizeof(*rzn1_adc));
rzn1_adc = iio_priv(indio_dev);
rzn1_adc->dev = dev;
ret = devm_mutex_init(dev, &rzn1_adc->lock);
rzn1_adc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rzn1_adc->regs))
return PTR_ERR(rzn1_adc->regs);
ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc1_vref_mV,
ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc2_vref_mV,
platform_set_drvdata(pdev, rzn1_adc);
ret = rzn1_adc_set_iio_dev_channels(rzn1_adc, indio_dev);
struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev);
return rzn1_adc_power(rzn1_adc, false);
struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev);
return rzn1_adc_power(rzn1_adc, true);