arch/arc/plat-hsdk/platform.c

211

writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0));

arch/arc/plat-hsdk/platform.c

217

writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1));

arch/arc/plat-hsdk/platform.c

234

writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));

arch/arc/plat-hsdk/platform.c

240

writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));

arch/arc/plat-hsdk/platform.c

246

writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));

arch/arc/plat-hsdk/platform.c

252

writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));

arch/arc/plat-hsdk/platform.c

258

writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));

arch/arc/plat-hsdk/platform.c

264

writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));

arch/arc/plat-hsdk/platform.c

270

writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));

arch/arc/plat-hsdk/platform.c

276

writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));

arch/arc/plat-hsdk/platform.c

282

writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));

arch/arc/plat-hsdk/platform.c

288

writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));