arch/arc/plat-hsdk/platform.c

209

writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));

arch/arc/plat-hsdk/platform.c

215

writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));

arch/arc/plat-hsdk/platform.c

233

writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));

arch/arc/plat-hsdk/platform.c

239

writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));

arch/arc/plat-hsdk/platform.c

245

writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));

arch/arc/plat-hsdk/platform.c

251

writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));

arch/arc/plat-hsdk/platform.c

257

writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));

arch/arc/plat-hsdk/platform.c

263

writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));

arch/arc/plat-hsdk/platform.c

269

writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));

arch/arc/plat-hsdk/platform.c

275

writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));

arch/arc/plat-hsdk/platform.c

281

writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));

arch/arc/plat-hsdk/platform.c

287

writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));