arch/arc/plat-hsdk/platform.c

212

writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0));

arch/arc/plat-hsdk/platform.c

218

writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1));

arch/arc/plat-hsdk/platform.c

236

writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));

arch/arc/plat-hsdk/platform.c

242

writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));

arch/arc/plat-hsdk/platform.c

248

writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));

arch/arc/plat-hsdk/platform.c

254

writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));

arch/arc/plat-hsdk/platform.c

260

writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));

arch/arc/plat-hsdk/platform.c

266

writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));

arch/arc/plat-hsdk/platform.c

272

writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));

arch/arc/plat-hsdk/platform.c

278

writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));

arch/arc/plat-hsdk/platform.c

284

writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));

arch/arc/plat-hsdk/platform.c

290

writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));