arch/arc/plat-hsdk/platform.c

210

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));

arch/arc/plat-hsdk/platform.c

216

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));

arch/arc/plat-hsdk/platform.c

235

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));

arch/arc/plat-hsdk/platform.c

241

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));

arch/arc/plat-hsdk/platform.c

247

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));

arch/arc/plat-hsdk/platform.c

253

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));

arch/arc/plat-hsdk/platform.c

259

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));

arch/arc/plat-hsdk/platform.c

265

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));

arch/arc/plat-hsdk/platform.c

271

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));

arch/arc/plat-hsdk/platform.c

277

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));

arch/arc/plat-hsdk/platform.c

283

writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));

arch/arc/plat-hsdk/platform.c

289

writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));