rsnd_mod_write
rsnd_mod_write(adg_mod, BRRA, adg->brga);
rsnd_mod_write(adg_mod, BRRB, adg->brgb);
rsnd_mod_write(mod, CMD_CTRL, 0x10);
rsnd_mod_write(mod, CMD_CTRL, 0);
rsnd_mod_write(mod, CMD_ROUTE_SLCT, data);
rsnd_mod_write(mod, CMD_BUSIF_MODE, rsnd_get_busif_shift(io, mod) | 1);
rsnd_mod_write(mod, CMD_BUSIF_DALIGN, rsnd_get_dalign(mod, io));
rsnd_mod_write(mod, CTU_CTUIR, 1);
rsnd_mod_write(mod, CTU_SWRSR, 0);
rsnd_mod_write(mod, CTU_CTUIR, 1);
rsnd_mod_write(mod, CTU_ADINR, rsnd_runtime_channel_original(io));
rsnd_mod_write(mod, CTU_CPMDR, cpmdr);
rsnd_mod_write(mod, CTU_SCMDR, scmdr);
rsnd_mod_write(mod, CTU_SVxxR(i, j), rsnd_kctrl_valm(ctu->sv[i], j));
rsnd_mod_write(mod, CTU_CTUIR, 0);
rsnd_mod_write(mod, CTU_SWRSR, 0);
rsnd_mod_write(mod, CTU_SWRSR, 1);
rsnd_mod_write(mod, DVC_DVUIR, 1);
rsnd_mod_write(mod, DVC_ADINR, adinr);
rsnd_mod_write(mod, DVC_DVUCR, dvucr);
rsnd_mod_write(mod, DVC_VRCTR, vrctr);
rsnd_mod_write(mod, DVC_VRPDR, vrpdr);
rsnd_mod_write(mod, DVC_VRDBR, vrdbr);
rsnd_mod_write(mod, DVC_DVUIR, 0);
rsnd_mod_write(mod, DVC_DVUER, 0);
rsnd_mod_write(mod, DVC_ZCMCR, zcmcr);
rsnd_mod_write(mod, DVC_VRPDR, vrpdr);
rsnd_mod_write(mod, DVC_VRDBR, vrdbr);
rsnd_mod_write(mod, DVC_DVUER, 1);
rsnd_mod_write(mod, DVC_SWRSR, 0);
rsnd_mod_write(mod, DVC_SWRSR, 1);
rsnd_mod_write(mod, DVC_DVUIR, 1);
rsnd_mod_write(mod, DVC_SWRSR, 0);
rsnd_mod_write(mod, DVC_VOLxR(i), val[i]);
rsnd_mod_write(mod, MIX_MDBDR, volD);
rsnd_mod_write(mod, MIX_MIXIR, 1);
rsnd_mod_write(mod, MIX_ADINR, rsnd_runtime_channel_after_ctu(io));
rsnd_mod_write(mod, MIX_MIXMR, rsnd_kctrl_vals(mix->ren));
rsnd_mod_write(mod, MIX_MVPDR, rsnd_kctrl_vals(mix->rup) << 8 |
rsnd_mod_write(mod, MIX_MIXIR, 0);
rsnd_mod_write(mod, MIX_MDBER, 0);
rsnd_mod_write(mod, MIX_MDBER, 1);
rsnd_mod_write(mod, MIX_SWRSR, 0);
rsnd_mod_write(mod, MIX_SWRSR, 1);
rsnd_mod_write(mod, MIX_MIXIR, 1);
rsnd_mod_write(mod, MIX_SWRSR, 0);
rsnd_mod_write(mod, MIX_MDBAR, volA);
rsnd_mod_write(mod, MIX_MDBBR, volB);
rsnd_mod_write(mod, MIX_MDBCR, volC);
void rsnd_mod_write(struct rsnd_mod *mod, enum rsnd_reg reg, u32 data);
rsnd_mod_write(mod, SRC_IFSVR, val);
rsnd_mod_write(mod, SRC_IFSVR, val);
rsnd_mod_write(mod, SRC_ROUTE_MODE0, route);
rsnd_mod_write(mod, SRC_SRCIR, 1); /* initialize */
rsnd_mod_write(mod, SRC_ADINR, adinr);
rsnd_mod_write(mod, SRC_IFSCR, ifscr);
rsnd_mod_write(mod, SRC_SRCCR, cr);
rsnd_mod_write(mod, SRC_BSDSR, bsdsr_table[idx]);
rsnd_mod_write(mod, SRC_BSISR, bsisr_table[idx]);
rsnd_mod_write(mod, SRC_SRCIR, 0); /* cancel initialize */
rsnd_mod_write(mod, SRC_I_BUSIF_MODE, i_busif);
rsnd_mod_write(mod, SRC_O_BUSIF_MODE, o_busif);
rsnd_mod_write(mod, SRC_BUSIF_DALIGN, rsnd_get_dalign(mod, io));
rsnd_mod_write(mod, SRC_INT_ENABLE0, int_val);
rsnd_mod_write(mod, SCU_SYS_STATUS0, val);
rsnd_mod_write(mod, SCU_SYS_STATUS1, val);
rsnd_mod_write(mod, SRC_CTRL, val);
rsnd_mod_write(mod, SRC_CTRL, 0);
rsnd_mod_write(mod, SRC_SWRSR, 0);
rsnd_mod_write(mod, SRC_SWRSR, 1);
rsnd_mod_write(mod, SRC_SRCIR, 1);
rsnd_mod_write(mod, SRC_SWRSR, 0);
rsnd_mod_write(mod, SSISR, 0);
rsnd_mod_write(mod, SSIWSR, ssi->wsr);
rsnd_mod_write(mod, SSICR, ssi->cr_own |
rsnd_mod_write(mod, SSICR, ssi->cr_own |
rsnd_mod_write(mod, SSICR, cr | ssi->cr_en);
rsnd_mod_write(mod, SSICR, cr); /* disabled all */
rsnd_mod_write(mod, SSI_INT_ENABLE, val);
rsnd_mod_write(mod, SSITDR, (*buf) << shift);
rsnd_mod_write(mod, reg, val);
rsnd_mod_write(mod, SSI_MODE, mode);
rsnd_mod_write(mod, adinr_reg,
rsnd_mod_write(mod, mode_reg,
rsnd_mod_write(mod, dalign_reg,
rsnd_mod_write(mod, HDMI0_SEL, val);
rsnd_mod_write(mod, HDMI1_SEL, val);
rsnd_mod_write(mod, SSI_CONTROL, 0x1);
rsnd_mod_write(mod, SSI_CONTROL, 0);
rsnd_mod_write(mod, reg, sys_int_enable);