Symbol: CP_INT_CNTL_RING0
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5443
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5445
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5447
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5449
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9077
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9083
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9244
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9290
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9335
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
2269
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
2271
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
2273
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
2275
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
6419
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
6421
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
6427
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
6429
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
6602
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
6648
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
6693
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1898
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1900
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1902
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1904
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
4742
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
4744
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
4750
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
4752
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
4919
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
4965
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5010
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
1547
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
1549
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
1551
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
1553
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
3760
WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
3783
WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
3848
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
3849
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
3850
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
3851
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
6389
WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
6449
WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
6460
WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
6526
WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2763
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2764
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2765
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2767
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
6004
WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
6102
WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
6138
WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
6171
WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
6197
WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
6206
WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1515
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1516
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1517
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
3226
WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
3266
WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
3305
WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
drivers/gpu/drm/radeon/cik.c
5760
u32 tmp = RREG32(CP_INT_CNTL_RING0);
drivers/gpu/drm/radeon/cik.c
5766
WREG32(CP_INT_CNTL_RING0, tmp);
drivers/gpu/drm/radeon/cik.c
6859
tmp = RREG32(CP_INT_CNTL_RING0) &
drivers/gpu/drm/radeon/cik.c
6861
WREG32(CP_INT_CNTL_RING0, tmp);
drivers/gpu/drm/radeon/cik.c
7037
cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
drivers/gpu/drm/radeon/cik.c
7217
WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
drivers/gpu/drm/radeon/si.c
5128
u32 tmp = RREG32(CP_INT_CNTL_RING0);
drivers/gpu/drm/radeon/si.c
5136
WREG32(CP_INT_CNTL_RING0, tmp);
drivers/gpu/drm/radeon/si.c
5933
tmp = RREG32(CP_INT_CNTL_RING0) &
drivers/gpu/drm/radeon/si.c
5935
WREG32(CP_INT_CNTL_RING0, tmp);
drivers/gpu/drm/radeon/si.c
6051
cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
drivers/gpu/drm/radeon/si.c
6083
WREG32(CP_INT_CNTL_RING0, cp_int_cntl);