rv_writel
rv_writel(val | 0x2, rtd->acp3x_base + reg_val);
rv_writel(adata->tdm_fmt, rtd->acp3x_base + frmt_reg);
rv_writel(val, rtd->acp3x_base + reg_val);
rv_writel(period_bytes, rtd->acp3x_base + water_val);
rv_writel(buf_size, rtd->acp3x_base + buf_reg);
rv_writel(val, rtd->acp3x_base + reg_val);
rv_writel(1, rtd->acp3x_base + ier_val);
rv_writel(val, rtd->acp3x_base + reg_val);
rv_writel(0, rtd->acp3x_base + mmACP_BTTDM_IER);
rv_writel(0, rtd->acp3x_base + mmACP_I2STDM_IER);
rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base +
rv_writel(PAGE_SIZE_4K_ENABLE, rtd->acp3x_base +
rv_writel(low, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val);
rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val
rv_writel(I2S_BT_TX_MEM_WINDOW_START,
rv_writel(I2S_SP_TX_MEM_WINDOW_START,
rv_writel(I2S_BT_RX_MEM_WINDOW_START,
rv_writel(I2S_SP_RX_MEM_WINDOW_START,
rv_writel(DMA_SIZE, rtd->acp3x_base + reg_dma_size);
rv_writel(acp_fifo_addr, rtd->acp3x_base + reg_fifo_addr);
rv_writel(FIFO_SIZE, rtd->acp3x_base + reg_fifo_size);
rv_writel(BIT(I2S_RX_THRESHOLD) | BIT(BT_RX_THRESHOLD)
rv_writel((rtd->xfer_resolution << 3),
rv_writel((rtd->xfer_resolution << 3),
rv_writel(adata->tdm_fmt, adata->acp3x_base + frmt_val);
rv_writel(val | 0x2, adata->acp3x_base + reg_val);
rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
rv_writel(BIT(BT_TX_THRESHOLD), rv_i2s_data->acp3x_base +
rv_writel(BIT(I2S_TX_THRESHOLD),
rv_writel(BIT(BT_RX_THRESHOLD), rv_i2s_data->acp3x_base +
rv_writel(BIT(I2S_RX_THRESHOLD),
rv_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
rv_writel(adata->pme_en, acp3x_base + mmACP_PME_EN);
rv_writel(1, acp3x_base + mmACP_SOFT_RESET);
rv_writel(0, acp3x_base + mmACP_SOFT_RESET);
rv_writel(0x01, acp_base + mmACP_EXTERNAL_INTR_ENB);
rv_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base +
rv_writel(0x00, acp_base + mmACP_EXTERNAL_INTR_CNTL);
rv_writel(0x00, acp_base + mmACP_EXTERNAL_INTR_ENB);