rv770_write_smc_soft_register
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_bbias, bb_dly);
rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_switch_lim, mclk_switch_limit);
rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_watermark_threshold,
rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_seq_index, 1);
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
rv770_write_smc_soft_register(rdev,
int rv770_write_smc_soft_register(struct radeon_device *rdev,