CR99
viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(CR99, VIACR, 0x08,
viafb_write_reg_mask(CR99, VIACR, 0x0F,
viafb_write_reg_mask(CR99, VIACR,
viafb_write_reg_mask(CR99, VIACR,
viafb_write_reg_mask(CR99, VIACR, 0x08,
dfp_low = viafb_read_reg(VIACR, CR99) & 0x0f;
viafb_write_reg_mask(CR99, VIACR, reg_val, 0x0f);
{VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew*/
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},