rtw_read8
mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) &
mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8;
coex_stat->kt_ver = u8_get_bits(rtw_read8(rtwdev, 0xf1), GENMASK(7, 4));
wl_reg_778 = rtw_read8(rtwdev, REG_BT_STAT_CTRL);
sys_lte = rtw_read8(rtwdev, 0x73);
wlk = !!(rtw_read8(rtwdev, REG_ARFR4) & BIT_WL_RFK);
rtw_read8(rtwdev, REG_AMPDU_MAX_TIME_V1);
val = rtw_read8(rtwdev, addr);
*data = rtw_read8(rtwdev, REG_EFUSE_CTRL);
bckp[2] = rtw_read8(rtwdev, REG_BCN_CTRL);
val = rtw_read8(rtwdev, REG_CR + 1);
val = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL + 2);
if (rtw_read8(rtwdev, REG_MCU_TST_CFG) == VAL_FW_TRIGGER)
ret = read_poll_timeout_atomic(rtw_read8, box_state,
ret = read_poll_timeout_atomic(rtw_read8, box_state,
val = rtw_read8(rtwdev, addr);
val = rtw_read8(rtwdev, addr);
orig = rtw_read8(rtwdev, addr);
orig = rtw_read8(rtwdev, addr);
rtw_read8(rtwdev, addr->rsvd);
rtw_read8(rtwdev, addr->avail);
value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
value8 = rtw_read8(rtwdev, REG_RF_CTRL);
value8 = rtw_read8(rtwdev, REG_H2C_INFO);
value8 = rtw_read8(rtwdev, REG_H2C_INFO);
value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1);
value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
return read_poll_timeout_atomic(rtw_read8, val, (val & mask) == target,
value = rtw_read8(rtwdev, REG_SYS_PW_CTRL);
value = rtw_read8(rtwdev, offset);
rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
if (rtw_read8(rtwdev, REG_CR) == 0xea)
(rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0)))
value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C;
bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1);
bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR);
tmp = rtw_read8(rtwdev, REG_BCN_CTRL);
value8 = rtw_read8(rtwdev, REG_CCK_CHECK);
fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL);
if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN)
if (rtw_read8(rtwdev, REG_SDIO_HSUS_CTRL) & BIT_HCI_RESUME_RDY)
id = rtw_read8(rtwdev, REG_C2HEVT);
hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
u8 v1 = rtw_read8(rtwdev, reg1->addr + i);
u8 v2 = rtw_read8(rtwdev, reg2->addr + i);
flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2);
flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2);
*value = rtw_read8(rtwdev, read_addr);
tmp = rtw_read8(rtwdev, RTK_PCI_CTRL + 3);
reg_bcn_work = rtw_read8(rtwdev, RTK_PCI_TXBD_BCN_WORK);
request = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
confirm = rtw_read8(rtwdev, rtwdev->hci.cpwm_addr);
ret = read_poll_timeout_atomic(rtw_read8, polling,
(rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0)
rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
val_ctx = rtw_read8(rtwdev, REG_CTX);
backup->mac8[i] = rtw_read8(rtwdev,
backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL);
ledcfg = rtw_read8(rtwdev, REG_LED_CFG);
if (rtw_read8(rtwdev, REG_CCK_CHECK) & BIT_CHECK_CCK_EN)
mac_reg_522 = rtw_read8(rtwdev, REG_TXPAUSE);
ledcfg = rtw_read8(rtwdev, REG_LED_CFG + 2);
val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
ret = read_poll_timeout(rtw_read8, iqk_chk, iqk_chk == IQK_DONE_8822C,
dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
reg_837 = rtw_read8(rtwdev, REG_BWINDICATION + 3);
if (rtw_read8(rtwdev, REG_CCK_CHECK) & BIT_CHECK_CCK_EN)
val8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN + 1);
if (!(rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_RAM_DL_SEL))
if (read_poll_timeout_atomic(rtw_read8, val8,
if (rtw_read8(rtwdev, REG_SYS_CFG1 + 3) & BIT(0))
val8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
reg_cr = rtw_read8(rtwdev, REG_CR);
if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_RAM_DL_SEL)
hci_opt = rtw_read8(rtwdev, REG_HCI_OPT_CTRL);
if (rtw_read8(rtwdev, REG_SYS_CFG2 + 3) == 0x20)
reason = rtw_read8(rtwdev, REG_WOWLAN_WAKE_REASON);
rtw_wow->txpause = rtw_read8(rtwdev, REG_TXPAUSE);
ret = read_poll_timeout(rtw_read8, check, !check, 1000,
(rtw_read8(padapter, EFUSE_CTRL + 2) & 0xFC));
readbyte = rtw_read8(padapter, EFUSE_CTRL + 3);
while (!(0x80 & rtw_read8(padapter, EFUSE_CTRL + 3)) && (tmpidx < 1000)) {
*data = rtw_read8(padapter, EFUSE_CTRL);
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 2);
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3);
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3);
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3);
return rtw_read8(Adapter, EFUSE_CTRL);
if (rtw_read8(padapter, 0x100) != 0xEA) {
MACBackup[i] = rtw_read8(pDM_Odm->Adapter, MACReg[i]);
tmpReg = rtw_read8(pDM_Odm->Adapter, 0xd03);
value = rtw_read8(padapter, offset);
value = rtw_read8(padapter, offset);
return rtw_read8(padapter, RegAddr);
originalValue = rtw_read8(padapter, regAddr);
trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX);
c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX);
c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xf0);
valid = rtw_read8(padapter, REG_HMETFR) & BIT(msgbox_num);
v8 = rtw_read8(padapter, REG_CR+1);
val8 = rtw_read8(padapter, REG_BCN_CTRL);
val8 = rtw_read8(padapter, REG_BCN_CTRL);
v8 = rtw_read8(padapter, REG_CR+1);
val8 = rtw_read8(padapter, REG_CR+1);
val8 = rtw_read8(padapter, REG_BCN_CTRL);
val8 = rtw_read8(padapter, REG_BCN_CTRL);
val8 = rtw_read8(padapter, REG_CR+1);
val8 = rtw_read8(padapter, bcn_ctrl_reg);
rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
val = rtw_read8(padapter, REG_LEDCFG2);
value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page;
io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
val8 = rtw_read8(padapter, REG_BCN_CTRL);
(rtw_read8(padapter, REG_CCK_CHECK_8723B)&~BIT_BCN_PORT_SEL)
tmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
val8 = rtw_read8(padapter, bcn_ctrl_reg);
val8 = rtw_read8(padapter, REG_BCN_CTRL);
val8 = rtw_read8(padapter, REG_BCN_CTRL);
val8 = rtw_read8(padapter, REG_BCN_CTRL);
val8 = rtw_read8(padapter, reg_bcn_ctl);
val8 = rtw_read8(padapter, reg_bcn_ctl);
val8 = rtw_read8(padapter, REG_BCN_CTRL);
tmp = rtw_read8(padapter, REG_MCUFWDL);
val8 = rtw_read8(padapter, MSR) & 0x0c;
val8 = rtw_read8(padapter, MSR) & 0x03;
rtw_write8(padapter, REG_RRSR+2, rtw_read8(padapter, REG_RRSR+2)&0xf0);
tmp = rtw_read8(padapter, REG_MCUFWDL);
val8 = rtw_read8(padapter, REG_TDECTRL+2);
val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2);
val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
*val = rtw_read8(padapter, REG_TXPAUSE);
val8 = rtw_read8(padapter, REG_TDECTRL+2);
val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
tmp_ps = rtw_read8(padapter, 0xa3);
tmp_ps = rtw_read8(padapter, 0xa0);
tmp = rtw_read8(padapter, REG_MCUFWDL+2);
if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) { /* 8051 RAM code */
tmp = rtw_read8(padapter, REG_MCUFWDL);
rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt);
tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL);
pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE);
pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2);
pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT+2);
pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1);
rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7)|BIT(7)); /* enable single pkt ampdu */
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8723B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7)));
value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
eeValue = rtw_read8(padapter, REG_9346CR);
val8 = rtw_read8(padapter, 0x4e);
req_fw_ps = rtw_read8(padapter, 0x8f);
*val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B);
value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
val = rtw_read8(padapter, REG_CR);
if (rtw_read8(padapter, 0x1e7) & 0x01)
val = rtw_read8(padapter, REG_MCUFWDL);
val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
val = rtw_read8(padapter, REG_RSV_CTRL + 1);
val = rtw_read8(padapter, REG_RSV_CTRL + 1);
val8 = rtw_read8(padapter, REG_HMETFR);
val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
val8 = rtw_read8(padapter, REG_CR);
if (rtw_read8(adapter, 0x100) == 0xEA)
extern u8 rtw_read8(struct adapter *adapter, u32 addr);